EMIB vs CoWoS — advanced-packaging interconnect, from first principles
Bottom line. EMIB and CoWoS exist to solve the same problem: routing dense die-to-die wiring that an organic package substrate cannot carry. They make opposite structural bets on how much silicon to use and where. Intel's EMIB puts silicon only at the seam between chiplets (a small embedded bridge), so it yields like a small die and has no reticle ceiling. TSMC's CoWoS, in its classic CoWoS-S form, puts every die on one large silicon interposer, which gives the densest routing but is reticle-limited and yields exponentially worse as it grows. Yield is the decisive economic variable, and it is why bridges are cheaper. The strategic twist for 2025-2026: TSMC's newest variant, CoWoS-L, embeds local silicon bridges of its own, so the contest is shifting from "bridge vs big interposer" to "bridge vs bridge" (EMIB-T vs CoWoS-L). Parent page: advanced-packaging.
The core bet (first principles)
Once a chip is split into chiplets, or HBM stacks are placed beside a GPU, you need thousands of fine, short connections between neighbours. Organic substrate trace pitch is too coarse. Silicon, patterned with chip-grade lithography, is fine enough. The entire EMIB-vs-CoWoS debate is about how much silicon you use, and where.
EMIB (Intel, volume since 2017) embeds a small silicon bridge die inside a cavity in an otherwise ordinary organic substrate. Silicon sits only where two chiplets meet; everywhere else is cheap organic. You can scatter as many bridges across a package as needed, and there is no reticle-size ceiling on the package. The original design deliberately omitted through-silicon vias (TSVs) to keep the bridge cheap, which had a cost: power had to route resistively around the bridge through the organic substrate rather than straight down through it. Intel's words (via SemiEngineering): EMIB "takes a lot less silicon area than an interposer... You can put as many bridges as you wish on a substrate... It doesn't have any reticle size limitation like a silicon interposer."
CoWoS (TSMC) is three structurally distinct things under one name:
- CoWoS-S places every die on a monolithic silicon interposer with TSVs. Densest routing, highest cost, bounded by the lithography reticle field (one exposure is 26mm x 33mm, about 858mm²). It scales only via reticle stitching to roughly 3.3-3.5x reticle (about 2,700-2,830mm²), beyond which the roughly 100µm-thick interposer risks delaminating or cracking.
- CoWoS-R swaps the silicon interposer for an organic carrier plus redistribution layers (RDL). Cheaper, lower I/O density.
- CoWoS-L uses an RDL interposer with an embedded Local Silicon Interconnect (LSI) bridge for the dense connections. Structurally this is TSMC's version of EMIB. SemiAnalysis states it plainly: CoWoS-L "is TSMC's equivalent to Intel's EMIB."
At a glance
| Dimension | EMIB / EMIB-T (Intel) | CoWoS-S (TSMC) | CoWoS-L (TSMC) |
|---|---|---|---|
| Structure | Small Si bridge in organic substrate | Monolithic Si interposer + TSV | RDL interposer + embedded Si bridge |
| Silicon used | Only at the die-to-die seam | Full package area | Only at the bridge regions |
| Reticle ceiling | None on package; bridges added as needed | ~3.3-3.5x reticle (~2,700-2,830mm²) | >5,000mm²; roadmap 5.5x then 9.5x |
| Yield character | Bridge yields like a small die (high) | Falls exponentially with interposer area | Bridge-limited, plus RDL yield |
| Cost per package (analyst est.) | Low hundreds of $ | ~$750 (H100-class) | ~$1,000-1,100 (B200-class) |
| Power delivery | Around bridge (classic); through TSV (EMIB-T) | Through interposer TSV | Through interposer |
| Status | EMIB in volume; EMIB-T fab rollout 2026 | Mature, sold out | Ramping for Blackwell / Rubin |
Confidence: structure and yield-character columns are well-sourced; cost and reticle-roadmap figures are analyst estimates and vendor targets (see caveats below).
Construction and process flow
EMIB (conventional flow, from Intel patent US10170428B2): build the organic substrate, laser-drill a cavity, bond the bridge die into it, laminate dielectric, drill vias, do semi-additive (SAP) lithography, apply solder resist, finish the surface. Intel's own patent names the laser cavity-drilling step as "a slow and costly operation... a significant bottleneck in the process flow." Several later Intel patents exist specifically to replace it, which independently confirms it as the cost and throughput baseline.
CoWoS-S: bond the dice onto the silicon interposer with micro-bumps (chip-on-wafer), thin the assembly until the TSVs are exposed (to roughly 100µm), form C4 bumps, singulate, then attach to the package substrate. This is the canonical CoWoS-S flow; CoWoS-R and CoWoS-L differ.
Yield economics (the decisive variable)
The governing physics is standard area-yield (Poisson / Murphy): at a fixed defect density, yield falls roughly exponentially with die area. A large silicon interposer is, for yield purposes, just a very large die.
SemiEngineering's Wang put the mechanism precisely: reticle stitching to a bigger interposer "will increase the die size and reduce the gross die per wafer and, based on the same defect density, would cause relatively poor yield." So CoWoS-S at large size yields only an estimated 60-70%. Note the nuance that survived verification: reticle stitching itself does not directly harm yield with good design rules; it harms yield indirectly by enlarging the interposer.
A bridge die is the opposite case. It is tiny, so it yields like any small die. Intel claims roughly 90% wafer utilization for bridges versus about 60% for large interposers (treat 90/60 as Intel's claimed figure, verified as a claim rather than independently audited).
But bridges move the risk rather than removing it. The verified expert view (TechSearch's E. Jan Vardaman): "one of the main challenges for the silicon bridge solutions is the yield of the interposer/substrate containing the bridge... yield is a critical factor." The bridge and the dice above it must align with very little margin. So EMIB trades large-interposer yield risk for bridge-alignment-and-embedding yield risk. This is also the open question hanging over EMIB-T: adding TSVs back into the bridge may erode the small-bridge yield advantage that is EMIB's core economic edge.
Cost per package
All figures are analyst estimates (Bernstein, JPMorgan, Morgan Stanley), not disclosed contract pricing. Hold at medium confidence.
- EMIB packaging: low hundreds of dollars per chip (Bernstein).
- CoWoS-S: about $750 for an H100-class part (roughly 814mm² die plus 5-6 HBM3 stacks).
- CoWoS-L: about $1,000-1,100 for a B200-class dual-die part, roughly a 40% premium over CoWoS-S.
- CoWoS-R: about $500-1,000, the cheapest variant.
- A fully processed CoWoS wafer runs about $10,000-12,000, and at large CoWoS-S sizes the interposer alone is 50-70% of total packaging cost.
The yield story drives the cost story: the interposer is most of the cost, and the interposer is the part whose yield collapses with size.
Scalability (reticle multiples; vendor roadmap targets)
CoWoS-S tops out near 3.3x reticle (about 2,700-2,830mm²) at 60-70% yield. CoWoS-L extends past 5,000mm², with TSMC targeting 5.5x in 2025-2026 and 9.5x (about 8,100mm², 12 HBM stacks) for 2027. Intel's EMIB-M is reportedly already at 6x reticle, with an 8x-by-2026 and 12x+-by-2028 roadmap; Intel has shown a conceptual 12x package with 16 compute dies and 24 HBM5 stacks at a 10,296mm² footprint. These are targets and concept designs, not shipped product. A common framing error is to pit "EMIB-M 6x" against "CoWoS-S 3.3x"; that cherry-picks the silicon-interposer ceiling. TSMC's comparable roadmap lives on CoWoS-L (5.5x to 9.5x), not CoWoS-S.
Who uses what, and capacity
TSMC CoWoS owns merchant AI accelerators and is supply-constrained. Capacity went from about 35,000 wafers/month (end-2024) to about 80,000 (end-2025), targeting roughly 130,000 by end-2026 via the AP7 (Chiayi) and AP8 (Tainan) fabs, and it remained oversubscribed. Nvidia booked more than 60% of total CoWoS capacity for 2025-2026; Blackwell and the upcoming Rubin require CoWoS-L. Other CoWoS customers include AMD (AMD) and Broadcom. The largest US-HQ OSAT and an Intel packaging partner is Amkor (AMKR); foundry-OSAT adjacency also runs through UMC (UMC) and ASE (2308).
Intel's counter is EMIB-T plus Foveros. EMIB-T reverses the original no-TSV decision: it adds TSVs to the bridge for vertical power delivery, plus MIM capacitors and a copper ground grid for isolation. Intel's disclosed ECTC 2025 specs (Rahul Manepalli): 45µm bump pitch heading to 35 and 25µm, about 0.25 pJ/bit, UCIe-A at 32 Gb/s+ per pin, HBM3 through a claimed HBM5, scaling to a 120mm x 180mm package with 38+ bridges. Fab rollout is slated for 2026. There is also reporting that Apple and Qualcomm have sought EMIB expertise, and that MediaTek is dual-sourcing EMIB and CoWoS. Intel-side supply-chain context: INTC, briefings/2026-04-26-intel-supply-chain.
Where Pink's tracked names touch this: AP Memory (6531) is an Intel EMIB first-qualified silicon-capacitor supplier with CoWoS-S/CoWoS-L design adjacency via TSMC; silicon-cap content sits inside the bridge and interposer (see silicon-capacitor-primer-2026-05-28). 268A and 5344 also carry EMIB/CoWoS exposure.
Strategic read — bridge vs bridge
The genuinely interesting development: now that CoWoS-L embeds local silicon bridges, the old "Intel's bridge vs TSMC's big interposer" framing is being superseded by a bridge-vs-bridge contest, EMIB-T against CoWoS-L, at the 9.5x-12x reticle scale targeted for 2027-2028. The question to watch is which approach yields and costs better once both are bridge-based and both carry TSVs, not the legacy EMIB-vs-CoWoS-S comparison that most casual coverage still uses.
What did not survive verification
The adversarial pass (3-vote, 2-of-3 to kill) killed five claims. Two are ones repeated confidently in casual coverage, so flag them:
- "EMIB has lower bandwidth / higher latency than CoWoS." Refuted (1-2). No defensible head-to-head bandwidth or latency number survived. Anyone asserting a clean bandwidth ranking between the two is over-claiming. This was the weakest-covered part of the question; the only hard density data points that held are EMIB-T's 45µm bump pitch, 0.25 pJ/bit, and 32 Gb/s.
- "EMIB costs 30-40% less than CoWoS." Refuted (1-2). The directional cost gap (low hundreds vs ~$750-1,100) holds, but the specific 30-40% figure does not, and much of its web sourcing circles back to one blog.
- A decade-long CoWoS bandwidth-scaling table with specific TB/s figures: refuted (0-3); the numbers and generation labels did not hold.
- "3.3x reticle is TSMC's limit": misleading; that is the CoWoS-S ceiling, not TSMC's overall capability.
- The AMD MI300 "designed on CoWoS-R, switched to CoWoS-S" story is SemiAnalysis's hedged inference, never confirmed by AMD or TSMC.
Honest read: construction, process-flow, and yield-mechanism claims are solid (several 3-0). Cost-per-package and capacity numbers are credible analyst estimates worth citing with the caveat. The bandwidth/latency head-to-head is genuinely unresolved by public sources. Forward roadmap numbers are vendor targets.
Sources
Primary: Intel patent US10170428B2 (EMIB conventional flow + laser-cavity bottleneck). Secondary / trade: Tom's Hardware (EMIB-T ECTC 2025 disclosure), SemiEngineering ("Using Silicon Bridges In Packages", "Reticle Stitching Bumps Up Silicon Interposer Costs"), WikiChip (CoWoS flow + reticle field), SemiAnalysis (CoWoS capacity constraints; CoWoS-L as TSMC's EMIB equivalent), TrendForce (MediaTek dual-sourcing; capacity), Astute Group (Nvidia 60% booking), Digitimes, TechPowerUp (Intel 16-die concept). Pink's own subscriptions that cover this: Viks ("Battle for Advanced Packaging: TSMC, Intel, Amkor", 2026-06-17) and Chipstrat ("Advanced Packaging: Intel's EMIB vs..."). Cost and yield figures are analyst estimates (Bernstein / JPMorgan / Morgan Stanley); interposer yields (60-70%) are modeling estimates, not vendor-disclosed.
Key links:
- Intel patent US10170428B2 — EMIB conventional flow + laser-cavity bottleneck (primary)
- SemiEngineering — Using Silicon Bridges In Packages — bridge construction, yield-of-the-bridge, Figure 1 source
- SemiEngineering — Reticle Stitching Bumps Up Silicon Interposer Costs — area-yield mechanism
- WikiChip — TSMC CoWoS — CoWoS flow + reticle field
- SemiAnalysis — AI Capacity Constraints: CoWoS and HBM — CoWoS-L as TSMC's EMIB equivalent; capacity
- Tom's Hardware — Intel EMIB-T heads for fab rollout — EMIB-T specs, cost spread, capacity
- TechPowerUp — Intel 16 compute dies + 24 HBM5 concept — large-package roadmap
- Viks — Battle for Advanced Packaging: TSMC, Intel, Amkor and Chipstrat — Advanced Packaging: Intel's EMIB vs CoWoS — Pink's own subscriptions
Method: deep-research harness, 2026-06-27. 6 search angles, 21 sources fetched, 102 claims extracted, top 25 adversarially verified (20 confirmed, 5 killed), 9 findings synthesized.