Foundry & Semiconductor Materials
Overview / thesis
Foundry and semiconductor materials is the layer of the chip stack where physics meets economics. Two distinct businesses live here: the foundries that print transistors on wafers, and the materials companies that engineer the wafers those transistors are printed on. Both sit in the most defensible positions in the value chain — the foundry because of the capital and process knowledge required to run a leading-edge fab, the materials supplier because a chip design locks in its substrate for the product's entire lifetime.
The investable "so what" is that this layer concentrates two things investors prize: structural moats (patents, process know-how, switching costs, installed base) and exposure to every major secular demand vector in technology at once. The same AI data-center buildout that drives demand for advanced logic also drives demand for the photonic substrates and optical transceivers that move data between accelerators. The same EV and renewables transition that needs power electronics needs compound-semiconductor substrates. A position in this layer is a way to own the AI and electrification cycles without picking which end-application wins.
Demand drivers
- AI data-center compute and optics. Every 800G / 1.6T optical transceiver in a data center needs photonics-SOI wafers. AI accelerators need leading-edge logic. This is the highest-conviction growth vector across both foundry and materials — it shows up as Soitec's Edge & Cloud AI segment growing +27% YoY and as Aixtron's AI-laser optoelectronics demand on the G10-AsP platform. See SOITEC, AIXA.
- 5G / RF front-end. RF filtering and front-end modules in smartphones consume RF-SOI substrates. This is a large, cyclical pool — RF-SOI was ~61% of SOITEC FY'25 revenue (the Mobile Comms segment) — and it tracks the smartphone inventory cycle.
- EV and industrial power electronics. Silicon carbide (SiC) and gallium nitride (GaN) power devices for EV powertrains and renewables drive demand for both engineered substrates and the MOCVD/CVD equipment that grows the device layers.
- Edge AI and automotive/industrial compute. Auto & Industrial was ~14% of SOITEC FY'25 revenue.
- 300mm wafer transition. The shift of compound-semi processes (notably GaN) from smaller wafers to 300mm is a multi-year platform upgrade that drives a fresh equipment and substrate cycle.
Opportunity sizing
The materials sub-pools are small in absolute dollars but high-share and growing with their end markets:
| Pool | Size today | Forward | Dominant player / share |
|---|---|---|---|
| SOI wafer market | ~$1.5B | $2.5–3.3B by 2029–2033 | SOITEC 70%+ share |
| MOCVD + SiC CVD equipment | ~$1.05B | growing with device markets | AIXA 77% MOCVD, 27% SiC CVD |
The thesis is not that these are large markets — they are not, relative to the trillion-dollar semiconductor whole. The thesis is that they are near-monopoly positions inside markets that compound with AI, 5G, and electrification, bought cyclically. Both anchor names traded through a cyclical downturn in 2025–2026, which is precisely when the asymmetric entries appear: a technology monopolist priced for permanent impairment is the setup worth owning. The discipline is to separate the moat (intact) from the cycle (transient) and from the valuation (the thing that actually determines your return).
How it works
A finished chip is transistors patterned onto a wafer. Two upstream things determine what that chip can do: the process node the foundry uses to pattern it, and the substrate the foundry patterns it onto. Both are engineered, both are bottlenecked, and both carry pricing power that flows from physics rather than branding.
The substrate: engineered wafers and the Smart Cut process
A commodity silicon wafer is cheap. An engineered wafer is not, because it has been re-architected at the atomic scale to give the transistors built on it a property they could not otherwise have — better isolation, lower leakage, lower parasitic capacitance, or compatibility with light.
The dominant technique is Smart Cut, a patented process best understood as an atomic scalpel: it cleaves a crystal-thin layer off a donor wafer and bonds that layer onto an insulating substrate. The result is a silicon-on-insulator (SOI) structure — a thin device-quality silicon film sitting on an insulating oxide, which electrically isolates the transistors from the bulk and cuts leakage and parasitics. The economics are a markup business: buy commodity silicon, apply patented process, sell the engineered substrate to foundries at a large premium. It is 100% product revenue, no services. See SOITEC, which holds 4,300+ patents around this process and 70%+ of the SOI wafer market.
The reason this is durable rather than a one-time sale is consumption. Wafers are consumed — every chip made eats substrate — so demand is continuous and recurring in practice, even though each sale is transactional. And once a chip is designed against a particular substrate, the design locks that substrate in for the product's full lifetime. That is the switching cost: re-qualifying a different wafer means re-spinning the chip.
Substrate variants map to end markets:
- RF-SOI — radio-frequency front-end and filtering for smartphones (5G). Largest pool by revenue, most cyclical (tracks smartphone inventory).
- Photonics-SOI (POI, piezoelectric-on-insulator) — substrates for silicon photonics: the optical engines inside 800G/1.6T transceivers in AI data centers. Highest-conviction growth. POI also serves RF filtering; an 11-customers-in-production / 13+-qualifying ramp shows the adoption curve.
- Engineered substrates for power — SiC-based structures (e.g., SmartSiC) for power electronics; a higher-risk capital bet (the SmartSiC line at Bernin IV took a €41M impairment, a signal of asset risk when a process bet runs ahead of demand).
Compound semiconductors and how their layers are grown
Silicon is not the right material for high-frequency, high-power, or light-emitting devices. For those you need compound semiconductors — gallium nitride (GaN), silicon carbide (SiC), indium phosphide (InP), gallium arsenide / arsenide-phosphide (AsP). These are built by growing the active material atom-by-atom onto a wafer rather than diffusing dopants into bulk silicon.
The growth method is MOCVD — metal-organic chemical vapor deposition — where precursor gases react at the wafer surface to deposit precisely controlled crystalline layers. Specialized CVD does the same for SiC. The machines that do this are the capital bottleneck. See AIXA, which holds 77% of the MOCVD market and 27% of SiC CVD, on 306 patent families. This is a capital-equipment business: ~80% one-time equipment sales, ~20% recurring aftermarket service — lumpier than substrates because customers buy machines in capex cycles, and a machine then lasts years (the opposite of consumed wafers).
Equipment maps to device families:
- GaN MOCVD — power electronics, RF; the 300mm GaN transition is the next platform cycle.
- SiC CVD — EV/renewables power; subject to overcapacity digestion (a glut that, once cleared, lets structural EV demand resume).
- AsP / optoelectronics (e.g., G10-AsP) — lasers for AI data-center optics, the fastest-growing equipment segment.
- InP and III-V optoelectronics — high-speed photonics and lasers.
Leading-edge logic: the process node
The other axis is the foundry process node itself — how small and how efficient the transistors are. The frontier is the 2nm CMOS logic platform: improvements in performance, power efficiency, and density versus prior nodes, delivered through new design rules and standard-cell libraries. This is the domain of the leading-edge foundries. (Source material here is thin — the 2nm reference is a stub with no extractable specs; treat node-level detail as a gap. See INTC, UMC, GFS.)
Why the economics hold
Across both axes the pattern repeats: a small number of suppliers, protected by patents and process know-how, selling into markets where the customer's own product is locked to the supplier's output. Substrates compound smoothly because they are consumed; equipment is lumpy because it is a capital good but is cushioned by ~20% recurring service. Through a full cycle, the substrate model carries lower revenue volatility — the most durable position in the layer.
Subsectors
The sector spans the foundries that pattern transistors and the materials/equipment players that supply the wafers and tools they depend on. The source material is deep on engineered substrates and compound-semi equipment, and thin on the pure-foundry node tiers — flagged honestly below.
Leading-edge / IDM foundry
The frontier of logic manufacturing: the most advanced process nodes (the 2nm CMOS logic platform and beyond), where performance, power efficiency, and transistor density are pushed each generation through new design rules and standard-cell libraries. Players are the integrated device manufacturers and pure-play leading-edge foundries — see INTC (IDM pursuing foundry). The angle is capital intensity as moat: only a handful of operators can fund and run a leading-edge fab, but the node race is unforgiving and the source detail here is a stub. (Thin — 2nm reference carries no extractable specs.)
Mature-node foundry
Trailing-edge logic on established nodes — high-volume, lower-capex-per-wafer, serving auto, industrial, and consumer where the latest node is unnecessary. See UMC, GFS (GlobalFoundries' differentiated/feature-rich mature platforms). The angle is durable utilization and pricing on depreciated equipment rather than node leadership. (Thin — no dedicated source content; named for coverage.)
Specialty / analog foundry
Process platforms tuned for analog, mixed-signal, RF, and power rather than digital logic — feature-rich rather than node-leading. See TSEM (Tower Semiconductor). The angle is differentiated process IP and long product lifecycles. (Thin — no dedicated source content; named for coverage.)
Silicon-photonics foundry (AMF / CPO)
Substrates and process for optical engines — the photonic layer that moves data optically inside and between systems, central to co-packaged optics (CPO) for AI data centers. The substrate angle is owned by photonics-SOI / POI (piezoelectric-on-insulator): every 800G/1.6T optical transceiver needs SOI wafers, and POI also serves RF filtering. See SOITEC — Edge & Cloud AI grew +27% YoY on this vector; 11 customers in production, 13+ qualifying; a Skyworks multi-year POI supply agreement (March 2026) validated the product. The companion equipment angle is the laser source: AI-laser demand on the G10-AsP optoelectronics platform, securing repeat orders from blue-chip customers — see AIXA. This is the single highest-conviction growth pocket in the sector.
Engineered substrates (SOI / SiC)
The Smart Cut franchise: silicon-on-insulator wafers for RF, photonics, and edge AI, plus SiC-based engineered substrates (SmartSiC) for power electronics. SOI market ~$1.5B today heading to $2.5–3.3B by 2029–2033, with SOITEC holding 70%+ share on 4,300+ patents — the strongest moat in semis (graded A+). The angle is monopoly economics on a consumed product: smooth recurring demand, design-locked switching costs. The SiC line is the higher-risk edge — the SmartSiC bet at Bernin IV took a €41M impairment, the cautionary note for the sub-area.
Compound-semi substrates (InP) and growth equipment
Indium phosphide and other III-V substrates for high-speed photonics and lasers, plus the MOCVD/CVD equipment that grows GaN, SiC, and InP device layers. See AXTI (AXT, InP/GaAs/Ge substrates) on the substrate side and AIXA on the equipment side — Aixtron holds 77% MOCVD share and 27% SiC CVD on 306 patent families, with segments split Power Electronics (GaN+SiC) 57%, Optoelectronics 23%, LED/Micro LED 15%, plus ~20% recurring service. The angle: own the picks-and-shovels of every compound-semi end market at once (AI optics, EV power, RF, LED), with the 300mm GaN transition as the next equipment cycle and SiC overcapacity digestion (clearing ~2027) as the cyclical overhang. (InP substrate player AXTI named for coverage; not detailed in source.)
Value chain
The chain runs commodity material → engineered substrate → growth/patterning equipment → foundry process → finished chip. The margin pools cluster at the two ends where IP and capital create scarcity: engineered substrates and process equipment upstream, leading-edge logic downstream. The middle (commodity silicon) is a price-taker.
Stage-by-stage
Commodity silicon (input). A price-taker. No moat, no pricing power — this is the cheap input that the substrate players buy and transform.
Engineered substrates. The first margin pool. A substrate maker buys commodity silicon, applies a patented process (Smart Cut), and sells to foundries at a large markup. 100% product revenue, no services. Economics: high gross margin protected by patents and design-lock switching costs; demand is smooth because wafers are consumed. SOITEC illustrates the pool — FY'25 gross margin 32.1%, EBIT margin 15.3%, net margin 10.3% on €891M revenue; ROIC ~15–17% at peak but falling to near zero (below WACC) at the cyclical trough. The bottleneck and moat are the same thing: 4,300+ patents and 70%+ share mean foundries have no alternative source.
Growth and patterning equipment. The second margin pool, and a structurally higher-margin one. The MOCVD/CVD toolmakers sell the machines that grow compound-semi layers. Economics: ~80% one-time equipment + ~20% recurring aftermarket service; revenue is lumpy (tied to customer capex cycles) but margins are richer. AIXA illustrates the pool — FY2025 gross margin 40%, EBIT margin 18%, net margin 15% on €557M revenue; ROIC ~25% at peak and still ~14% (above WACC) at the trough. R&D runs ~15% of revenue (€81M). The moat is installed base plus 77% MOCVD / 27% SiC CVD share on 306 patent families.
Foundry process / leading-edge logic. The downstream margin pool, gated by capital intensity — only a few operators can fund a leading-edge fab on the 2nm CMOS platform. This is where the substrates and the grown layers get patterned into chips. (Source material thin on per-stage foundry economics — node detail is a stub. See INTC, UMC, GFS, TSEM.)
Margin-pool comparison (the two well-documented stages)
| Stage | Gross margin | EBIT margin | Trough ROIC | Revenue character |
|---|---|---|---|---|
| Engineered substrates (SOITEC) | 32.1% | 15.3% | ~0% (below WACC) | Smooth — consumed product, design-locked |
| Growth equipment (AIXA) | 40% | 18% | ~14% (above WACC) | Lumpy — capital good + 20% recurring service |
The equipment stage earns higher steady-state margins and holds ROIC above cost of capital even at the trough; the substrate stage is more cyclically fragile at the bottom but carries lower through-cycle volatility because its product is consumed continuously. Substrates trade smoothness for thinner margins; equipment trades lumpiness for richer margins and a fortress balance sheet.
Bottlenecks
- Patent / process IP — the gate on both upstream pools. Smart Cut (substrate) and MOCVD know-how (equipment) cannot be cloned quickly; the Chinese-competitor threat is a 5–10 year horizon on the substrate side, and AMEC (Chinese state-backed) is the nearer-term challenger on equipment.
- Capital intensity — the gate on the foundry stage; leading-edge fabs are a barrier few can clear.
- Customer capex cycles — the timing bottleneck for equipment demand; substrate demand is gated instead by end-market inventory cycles (smartphone RF, auto).
- Process bets running ahead of demand — the SmartSiC €41M impairment is the cautionary case: building capacity for a substrate market before the demand arrives destroys returns.
Where the value accrues
Upstream IP holders capture disproportionate margin because their customers (foundries) are locked in by design qualification and have no second source. The single richest sub-pool is photonics for AI optics — photonics-SOI substrates (SOITEC) and the AI-laser equipment that pairs with them (G10-AsP, AIXA) — because it sits at the intersection of the highest-growth end market (AI data center) and the most defensible upstream positions.
Players
The two best-documented names in the vault for this sector are the European monopolists profiled head-to-head: SOITEC on the substrate side and AIXA on the equipment side. The foundry-tier names are linked for coverage but carry no dedicated source detail yet.
SOITEC — engineered-substrate monopolist
Soitec S.A. (EPA: SOI), Semiconductor Materials. Makes the engineered wafers that go into chips via the patented Smart Cut process. The deepest moat in semis (graded A+): 4,300+ patents, 70%+ share of the SOI wafer market. Revenue mix FY'25: Mobile Comms ~61% (RF-SOI), Edge & Cloud AI ~24%, Auto & Industrial ~14%. Positioning is sole-source: customers have no alternative, so moderate customer concentration (top 5 likely 60%+) is mitigated by monopoly. Buying back shares (2.6% TTM reduction), no dividend. Key overhangs: CEO Pierre Barnabé departing March 31, 2026 with no named successor (CTO since 1993 and COO since 2006 provide operational continuity), and the SmartSiC bet at Bernin IV (€41M impairment). Growth vectors: photonics-SOI for AI optics (+27% YoY), RF-SOI recovery (Q3 FY'26 +18% sequential), POI adoption (Skyworks multi-year agreement March 2026; 11 in production, 13+ qualifying).
AIXA — compound-semi equipment monopolist
Aixtron SE (XETRA: AIXA), Semiconductor Equipment. Makes the MOCVD machines that grow compound-semi layers (GaN, SiC, InP) atom-by-atom. Moat graded A- (very strong): 306 patent families, 77% MOCVD share, 27% SiC CVD share, plus installed-base lock-in. Revenue mix: Power Electronics (GaN+SiC) 57%, Optoelectronics 23%, LED/Micro LED 15%, with Service ~20% of total; geographic Asia 60% / Americas 20% / Europe 20%, no single customer >10%. Fortress balance sheet: zero debt, €225M net cash plus €200M undrawn revolver, 88% equity ratio. Capital-disciplined — the ~€100M Innovation Center (300mm GaN capability) is now operational, flat share count, token €0.15 dividend, proactive headcount cuts (January 2026). Growth vectors: AI-laser optoelectronics (G10-AsP, repeat blue-chip orders), SiC capacity digestion (100th G10-SiC delivered in 3 years; overcapacity likely clears 2027), 300mm GaN transition. EU Chips Act beneficiary. Near-term watch: Q1 2026 results April 30. Note: Aixtron is an equipment maker, included here as the comparison anchor and compound-semi enabler, not a foundry.
Foundry-tier names (coverage links, thin source detail)
- INTC — Intel, IDM pursuing leading-edge foundry. (No dedicated source content.)
- UMC — United Microelectronics, mature-node foundry. (No dedicated source content.)
- GFS — GlobalFoundries, differentiated/feature-rich mature-node foundry. (No dedicated source content.)
- TSEM — Tower Semiconductor, specialty/analog foundry. (No dedicated source content.)
- AXTI — AXT Inc., compound-semi (InP/GaAs/Ge) substrates. (No dedicated source content.)
Soitec vs. Aixtron — comparison and composite scorecard
The two are both European mid-cap monopolists in their niches, both in cyclical downturns, both riding AI-driven tailwinds — but with opposite recent trajectories. Soitec peaked near €59 and pulled back ~25%; Aixtron nearly doubled since year-end 2025.
At-a-glance (March 2026):
| Metric | SOITEC | AIXA |
|---|---|---|
| Market Cap | €1.58B | €3.70B |
| Enterprise Value | €1.72B | €3.47B |
| Price (Mar 2026) | €44.17 | €32.60 |
| 52-Week Range | €22.62–€59.30 | €8.45–€35.07 |
| 52-Week Performance | ~+95% from low | ~+286% from low |
| YTD Performance | -25% (from ~€59 peak) | +88% (from ~€17 year-end 2025) |
| Dividend Yield | 0% | 0.5% (€0.15/share) |
| Beta (5Y) | 1.44 | ~1.5 (est.) |
| Moat grade | A+ (4,300+ patents, Smart Cut) | A- (306 patent families, 77% MOCVD) |
Financials:
| Metric | SOITEC | AIXA |
|---|---|---|
| Revenue (LTM) | €891M (FY'25) | €557M (FY2025) |
| Revenue Growth YoY | -9% | -12% |
| Revenue Growth NTM est. | -35% (FY'26E ~€583M) | -7% (FY2026E ~€520M) |
| Gross Margin | 32.1% | 40% |
| Operating Margin | 15.3% | 18% |
| Net Margin | 10.3% | 15% |
| EPS (LTM) | €2.57 | €0.76 |
| FCF (LTM) | €26M | €182M (WC-distorted; normalized ~15% margin) |
| Net Debt (Cash) | €145M net debt (0.5x EBITDA) | €225M net cash |
| Cash & Equivalents | €808M | €225M + €200M undrawn revolver |
| ROIC | ~15–17% peak; ~0 trough | ~25% peak; ~14% trough |
Valuation:
| Multiple | SOITEC | AIXA |
|---|---|---|
| P/E (LTM) | 17.2x | 42.9x |
| P/E (NTM) | N/M (near-zero earnings) | ~47–54x |
| EV/EBITDA (LTM) | 5.8x | 29.7x |
| EV/EBITDA (NTM) | ~11.3x | ~32x |
| EV/Revenue (LTM) | 1.9x | 6.2x |
| P/FCF | 61x (depressed) | 20x (WC-distorted) |
| P/B | 1.1x | ~4.1x |
| vs. own 5Y avg EV/EBITDA | -10 to -20% discount (justified) | +80–110% premium (not justified) |
Composite scorecard (weighted):
| Dimension | Weight | SOITEC | AIXA |
|---|---|---|---|
| Business Quality | 20% | 4.5/5 | 4.0/5 |
| Financial Health | 15% | 3.5/5 | 4.5/5 |
| Growth | 20% | 4.0/5 | 3.5/5 |
| Valuation | 20% | 4.5/5 | 1.5/5 |
| Quality & Capital Allocation | 10% | 3.0/5 | 4.0/5 |
| Risk (inverted) | 10% | 3.0/5 | 2.5/5 |
| Technical Timing | 5% | 3.5/5 | 2.0/5 |
| Weighted Score | 100% | 3.82 | 3.14 |
Verdict (March 2026): SOITEC ranked BUY (3.82) — deeper moat, deeper trough (revenue -47% peak-to-trough vs. Aixtron's -18%), dramatically cheaper (5.8x vs. 29.7x EV/EBITDA), asymmetric entry after the €59→€44 pullback; forward 3Y revenue CAGR 15–18%. AIXA ranked WATCH (3.14) — excellent business (cleaner balance sheet, higher through-cycle ROIC, no CEO drama) but priced for full recovery plus re-rating; the stock has nearly 4x'd and sits above the ~€27–28 analyst target and the €20–22 fair-value range. Suggested play: buy Soitec now, limit order on Aixtron at €22–25.
Monitor
Dated developments, catalysts, and watch-items consolidated from the March 2026 Soitec vs. Aixtron showdown. Company-specific detail lives on SOITEC and AIXA; this is the sector-level watch frame.
Catalysts and dated events
- March 10–13, 2026 — pricing snapshot for the comparison: SOITEC €44.17 (down ~25% from ~€59 peak), AIXA €32.60 (up ~286% from 52-week low).
- March 2026 — SOITEC signs Skyworks multi-year POI (piezoelectric-on-insulator) supply agreement, validating the photonics/RF-filter product; 11 customers in production, 13+ qualifying.
- March 31, 2026 — SOITEC CEO Pierre Barnabé departs with no named successor. Key-person / strategic-direction risk, including the fate of the SmartSiC bet. Operational continuity from CTO (since 1993) and COO (since 2006).
- April 30, 2026 — AIXA Q1 2026 results. Primary near-term catalyst; a disappointment is the trigger for a correction given the ~4x run and 30x EV/EBITDA.
- January 2026 — AIXA proactive headcount reductions (cost discipline ahead of the down year).
- Q3 FY'26 — SOITEC RF-SOI showed +18% sequential improvement, the first sign the smartphone inventory correction is bottoming.
Structural watch-items
- SiC overcapacity digestion — the glut likely clears around 2027, after which structural EV/renewables SiC demand resumes. Watch for inventory normalization across the compound-semi chain. AIXA delivered its 100th G10-SiC in 3 years.
- 300mm GaN transition — the Innovation Center (now operational) enables next-gen 300mm GaN; a multi-year platform upgrade that should drive a fresh equipment cycle. Watch order momentum.
- AI optics ramp — photonics-SOI (SOITEC, +27% YoY) and AI-laser equipment (G10-AsP, AIXA) are the highest-conviction vector; watch transceiver demand (800G → 1.6T) as the demand proxy.
- RF-SOI / smartphone inventory cycle — the swing factor for 61% of SOITEC revenue; watch sequential RF-SOI recovery.
- SmartSiC asset risk — after the €41M impairment, watch for further write-downs or a strategic decision on the Bernin IV line under the new SOITEC CEO.
- Competitive disruption — Chinese SOI threat on a 5–10 year horizon; AMEC (Chinese state-backed) growing on the MOCVD/equipment side — nearer-term but still low-to-moderate.
- Valuation overshoot (AIXA) — stock above the ~€27–28 analyst average and the €20–22 fair-value range; FY2026 guidance still -7% YoY. Little margin for error at 43x trailing / 30x EV/EBITDA.
Watch-item: leading-edge node cadence
The 2nm CMOS logic platform and node transitions at the foundries (INTC, UMC, GFS, TSEM) are the downstream demand setter but are not covered in the current sources. (Thin — no dated developments in source material; flag as a coverage gap.)
Sources
Consolidated source files
KB/wiki/_compare/soitec-vs-aixa-showdown.md— "Stock Showdown: Soitec vs. Aixtron" (skill: compare; dated 2026-03-22). Primary source for this page: business models, financials, valuation, growth, risk, capital allocation, technical setup, composite scorecard, and the full set of catalysts. Authored research, not an external publication.KB/wiki/tsmc-2nm-platform.md— "TSMC's New, Industry-Leading 2nm CMOS Logic Platform" (author/firm: TSMC, dated 2024-10-08, src/tech-paper). Indexed stub only — generic capability bullets and a source pointer, no extractable specs. Contributed the leading-edge / 2nm node framing; flagged thin throughout.
Source authors / publications
- TSMC — author of the 2nm CMOS logic platform tech-paper.
- Data sources cited within the showdown: Soitec FY'25 results, H1 FY'26 and Q3 FY'26 reports; Aixtron FY2025 annual report; MarketScreener; StockAnalysis; TipRanks; Stockopedia; company IR presentations. Prices as of March 10–13, 2026; figures in EUR unless noted.
- Company IR: SOITEC (soitec.com/home/investors), AIXA (aixtron.com/investoren).
Coverage gaps
No dedicated source material for the leading-edge/IDM (INTC), mature-node (UMC, GFS), specialty/analog (TSEM), or InP-substrate (AXTI) sub-areas — these are linked for coverage only. See index for canonical ticker pages.
Consolidation queue (merged 2026-05-30 — section-scoped rebuild)
Industry-wide content folded in from these source files. They stay live pending Pink's archive confirm.
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_compare/soitec-vs-aixa-showdown.md - [ ]
tsmc-2nm-platform.md