Intel Corporation (INTC)
🔴 Live $95.72 (IBKR) · 2026-09-05 · research written 2026-03-09 Consensus $75–$200 (mean $116, 12mo, Yahoo consensus (41 analysts)) · 2026-09-05 your target >$80 (own-DD, 2-4yr) — now past (+20%)
Identity
| Field | Value |
|---|---|
| Company | Intel Corporation |
| Exchange | NASDAQ: INTC |
| Market Cap | ~$217B (Mar 2026) |
| Shares Outstanding | 4.53B |
| CEO | Lip-Bu Tan (appointed Mar 2025) |
| Sector | Semiconductor — IDM / Foundry |
| Price | $43.34 (Mar 9, 2026) |
| 52-Week Range | $17.67 -- $54.60 |
One-sentence: Intel designs and manufactures processors for PCs, servers, and data centers -- and is trying to become the Western world's answer to TSMC by building a foundry that makes chips for other companies.
Thesis
Intel under Lip-Bu Tan is a high-risk/high-reward turnaround with genuinely asymmetric outcomes. If 18A/14A process technology achieves competitive yields and attracts external foundry customers, Intel could re-rate from a value trap to a strategic national champion trading at a semiconductor-grade multiple. The $37.4B cash hoard, CHIPS Act backing, and Tan's credibility provide a margin of safety. The stock has already rallied 209% from its mid-2025 lows, but if the turnaround succeeds, there's significantly more upside.
Why this might work: Turnaround / special situation -- catalyst will unlock value. The U.S. government placed a massive bet on Intel's success through $7.86B in CHIPS Act grants plus $8.9B in additional funding, took a 9.9% equity stake, and Nvidia ($5B) and SoftBank ($2B) invested. This level of institutional backing is extraordinary.
Single most important thing that must go right: Intel 18A process node must achieve competitive yields (industry-standard levels expected by 2027) and win at least one major external foundry customer.
Expected holding period: 2--4 years. Multi-year thesis requiring patience and quarterly monitoring.
Exit criteria: Sell if 18A yields remain non-competitive through 2027 (thesis broken), if DCAI market share drops below 50% (AMD/ARM taking too much), or at $80+ (near 2x from here).
Business
Revenue Model & Key Segments
| Segment | FY2025 Revenue | % of Total | YoY Change |
|---|---|---|---|
| Client Computing Group (CCG) | $32.23B | ~61% | +6.4% |
| Data Center & AI (DCAI) | $16.92B | ~32% | +32.0% |
| Intel Foundry (IFS) | $17.83B | ~34% | +1.6% |
| All Other (Mobileye, Altera residual) | $3.56B | ~7% | -6.8% |
Segment percentages include inter-segment revenue (Foundry largely serves internal customers), so they exceed 100%.
CCG is the cash cow. DCAI is the growth engine (+32% YoY). Intel Foundry is the strategic bet -- $17.8B in revenue but operating at -50% margins, hemorrhaging ~$2.5B per quarter. The foundry loses roughly $7B a year.
Turnaround Strategy Under Lip-Bu Tan
- Manufacturing renaissance: Recommitting to in-house fabrication; 18A node in risk production, Panther Lake (first 18A product) now shipping
- Foundry-as-a-service: Positioning Intel Foundry as a credible alternative to TSMC for external customers; secured Nvidia/SoftBank as strategic investors
- Cost optimization: Targeting $17B non-GAAP OpEx in 2025, further reduction to $16B in 2026; aggressive middle-management cuts
- Portfolio simplification: Sold 51% of Altera to Silver Lake ($4.3B), monetized Mobileye stake ($900M+), divesting non-core assets
- AI catch-up: Building custom Xeon CPUs integrated with Nvidia's NVLink; investing in AI accelerator roadmap
Competitive Position
Moat: weakened but not destroyed.
Retained:
- x86 architecture dominance (shrinking)
- Only Western-allied company with cutting-edge fabs -- geopolitical strategic asset
- Deep U.S. government support (CHIPS Act, equity stake)
- Massive installed base in enterprise/data center (billions of x86 processors)
Eroding:
- AMD has taken ~34% server CPU share and growing; ~35% desktop, ~25% laptop
- ARM-based alternatives (Qualcomm, Apple Silicon, AWS Graviton, Microsoft Cobalt) nibbling at x86
- Foundry has zero external track record -- TSMC holds 66% global share
- Samsung's cautionary tale: similar variation issues at 3nm GAA, lost all external customers
vs. AMD: AMD's 3-year forward revenue CAGR forecast is 34.8% vs Intel's 8.1%. AMD's fabless model (TSMC manufacturing) provides cost advantage. AMD EPYC now approaching 30% server share.
vs. NVIDIA: Nvidia dominates AI/data center GPU market; Intel's AI accelerators (Gaudi) have negligible share. Nvidia invested $5B in Intel -- strategic partnership, not direct competition in CPUs. Custom Xeon + NVLink integration signals collaboration.
vs. TSMC: TSMC holds ~66% of global foundry market share. TSMC's 2nm enters mass production in 2026; Intel's 18A is roughly equivalent. TSMC's A14 (1.4nm-class) node expected 2028 vs Intel's 14A risk production 2027.
Process Node Progress
- Intel 18A: Risk production complete; Panther Lake shipping; yields improving but won't reach industry standard until 2027
- Intel 14A: Scheduled for risk production in 2027; uses High-NA EUV (first in industry); potential to leapfrog TSMC
- Key risk: CEO Tan reportedly reconsidering the fate of 18A -- may deprioritize in favor of 14A for external customers
Roadmap & External Customer Pipeline (per company data via GFHK, May 2026)
Process node cadence: 18A (2H25) → 18A-P (2H26) → 14A (2H27).
Intel internal products:
| Period | PC | Server |
|---|---|---|
| 2H25 | Panther Lake | -- |
| 1H26 | Wildcat Lake | -- |
| 2H26 | Nova Lake (TSMC N2) | Clearwater Forest |
| 1H27 | -- | Diamond Rapids |
| 2H27 | Razor Lake (TSMC N2) | Coral Rapids |
Note: Nova Lake and Razor Lake (PC) are slated to be fabbed at TSMC N2, not Intel's own nodes -- a tell that Intel's own client roadmap doesn't fully trust 18A-P / 14A for the highest-volume consumer parts.
External foundry clients (front-end + EMIB advanced packaging):
| Period | Front-End | EMIB |
|---|---|---|
| 2H26 | USG Program | -- |
| 2H27 | Apple M (on 18A-P), NVDA gaming | Google TPU v8e |
| 2H28 | Apple Smartphone SoC, NVDA, AMD, Ethernet Switch, Tesla | Meta CPU (TBD) |
Why this matters for the thesis: This list -- if it holds -- directly attacks the bearish variation thesis (see next section). The leading indicators called out at line 128 included "Mobile design win (any smartphone SoC commitment directly refutes 'can't do mobile')." The slide explicitly puts an Apple smartphone SoC in 2H28 and an Apple M-series part on 18A-P in 2H27. Apple has the most stringent process requirements in the industry; a real Apple win on 18A-P would invalidate the "wide PVT corners can't serve mobile" objection.
Source caveat: GFHK is a Chinese-language sell-side / industry research deck. Treat as a credible bull-case roadmap, not Intel-confirmed. Apple-on-Intel and NVDA-on-Intel rumors have circulated for two years; only the Microsoft and Amazon test-chip wins on 18A are publicly confirmed by Intel itself. Verify any line item before treating it as a catalyst -- look for: (1) Intel earnings-call language naming the customer, (2) tape-out press releases, (3) IFS revenue guidance raises.
Things to watch from this roadmap specifically:
- Any Intel/Apple confirmation around the 2H27 Apple M (18A-P) window -- would be the single most powerful catalyst on this list
- Whether Nova Lake / Razor Lake stay on TSMC N2 or migrate to internal fabs (insourcing = vote of confidence in 18A-P)
- Google TPU v8e using EMIB advanced packaging in 2H27 -- Intel's packaging business may be the easier sell than its front-end fab
- USG Program (2H26) is the obvious anchor tenant; the question is whether commercial customers actually follow
The 18A Process Variation Problem (Discord Deep-Dive)
This is the most important technical nuance in the Intel thesis. An insider-ish discussion (parakeetfour, likely works in chip design) surfaced serious concerns about Intel 18A's process variation -- and the implications cut directly into whether the foundry strategy can work.
The core problem: PVT corners are wide. When chips come off the fabrication line, transistor performance varies -- some chips run fast (FF corner), some slow (SS corner), with a typical target in the middle (TT). The range of this variation is described by process corners. Parakeetfour claims Intel's variation range is big -- chips coming off 18A vary wildly in performance characteristics. The "transistor cells are only designed for yield harvesting" comment suggests Intel optimized the process to get something working off each wafer, rather than optimizing for tight parametric control.
Why this matters -- the speed binning question: Large variation is survivable if you can speed-bin -- test each chip, see how fast it actually runs, and sell it at the appropriate tier (i3 vs i5 vs i7). Datacenter CPUs can do this. But many products cannot speed bin:
- PHYs and fixed-frequency IP -- SerDes, DDR interfaces need to hit exact frequencies. You can't sell a "slow" PCIe PHY.
- Mobile SoCs -- Apple, Qualcomm, MediaTek can't sell "A17 Slow Edition." There's almost no market for inferior SKUs. Mobile has hard power ceilings.
- Modems, DSPs -- Need precise timing, less tolerant of variation.
- Networking/Infrastructure ASICs -- Broadcom, Marvell custom silicon. If your 112G PAM4 PHY doesn't hit spec, the chip is scrap.
- Automotive -- More stringent than consumer. Functional safety requirements mean wide process corners = more design margin, larger die, higher cost.
The foundry TAM funnel problem:
Total Foundry TAM: ~$150B and growing
- Advanced nodes (<7nm): ~$80B
- Can tolerate wide variation: maybe $15-20B?
- Willing to use non-TSMC: ???
- Willing to use Intel specifically: ???
Each filter shrinks the addressable market. Even if Intel executes perfectly on 18A yield ramp, the type of customers they can serve may be structurally limited to datacenter CPUs and large AI accelerators -- a narrow slice of the foundry TAM.
TSMC's real moat isn't density -- it's consistency. Their N3E process corners are tight enough that fabless companies can design once and get predictable results. That's why Apple keeps paying premium pricing despite TSMC's near-monopoly position.
What would change the picture: (1) Intel dramatically tightens variation on 18A-P or 14A -- but the "yield harvesting" design philosophy suggests this might be architectural, not just tuning. (2) Geopolitical forcing function -- US government mandates domestic production. (3) A lighthouse customer like Qualcomm tapes out a production chip and it works.
Leading Indicators to Watch
Bullish (variation thesis is wrong):
- External customer tape-out announcement (real company, not test chip)
- Mobile design win (any smartphone SoC commitment directly refutes "can't do mobile")
- Panther Lake hits 6GHz+ with reasonable power
- Intel raises external foundry revenue guidance (currently $15B by 2030)
- Clearwater Forest server CPU ships on time
Bearish (variation thesis is right):
- No new foundry customer announcements beyond test chips
- Panther Lake clock speed reductions or TDP increases
- Intel pivots messaging to "different" not "better" -- emphasizing packaging, sovereignty over process leadership
- Design wins only in captive + government applications
- Aggressive 14A pull-in before proving 18A
- Earnings commentary hedging: "yield learning continues" without specifics
Smoking guns: Qualcomm's next foundry decision (if they conspicuously ignore Intel while talking supply diversification -- damning). MediaTek's choice (most likely to try Intel if economics work; no engagement by 2026 = market has spoken). Apple will never use Intel Foundry, but watch how aggressively they lock up TSMC N2/A16 capacity.
Quantitative monitors: IFS quarterly external revenue (currently ~$900M/quarter, mostly internal). CapEx allocation shifts between 18A capacity and packaging (Foveros, EMIB). Wafer price discounts (steep discounts = can't compete on technology alone).
Verification Channels
- IEDM / VLSI Symposium papers: Look for tight bell curves (variation solved) vs emphasis on "design enablement" without parametric distributions (yellow flag)
- Patent filings: Heavy patenting around adaptive voltage/frequency scaling, on-die variation sensors, and binning algorithms would corroborate variation as a known issue
- EDA vendor commentary (Synopsys, Cadence, Siemens): Listen for "design enablement challenges" and how they characterize 18A vs N3/N2 tool readiness
- Silicon lottery data: When Panther Lake launches, overclockers will reveal clock speed distribution and voltage requirements across samples. Wide spread = variation confirmed.
- TechInsights/SystemPlus teardowns: Direct measurement of gate length variation, nanosheet dimension consistency, metal pitch uniformity
Management
CEO: Lip-Bu Tan
Appointed March 2025; former CEO of Cadence Design Systems (built it from a struggling EDA company into an $85B+ market cap powerhouse) and former Intel board member. The Cadence track record is the strongest argument for the bull case -- Tan has done a turnaround before, in a related industry, and it worked spectacularly.
Skin in the game:
- Bought $25M in Intel shares at ~$37.92 shortly after appointment; additional $2.5M purchase recorded
- Equity grants (Feb 2026): 306,692 PSUs (up to 200% payout) + 468,087 stock options
- Compensation package could exceed $400M if turnaround succeeds (stock price triple target)
- Total insider ownership ~0.05% (~$55M worth) -- low by absolute standards, but Tan's compensation is heavily equity-linked
Board changes: Chair Frank Yeary stepping down after 17 years (announced March 4, 2026). Leadership reshuffling under Tan to drive turnaround. Average management tenure is short (new team) -- governance transition risk.
Assessment: B+. Tan is credible and aligned via equity. But it's early innings and the team is new.
Financials
Q4 2025 Results
| Metric | Q4 2025 | Notes |
|---|---|---|
| Revenue | $13.7B | -4% YoY |
| Non-GAAP Gross Margin | 37.9% | ~140bps above guidance |
| GAAP EPS | ($0.12) | Still negative |
| Non-GAAP EPS | $0.15 | -- |
Full-Year 2025
| Metric | FY2025 | FY2024 | Change |
|---|---|---|---|
| Revenue | $52.9B | $53.1B | -0.5% |
| Non-GAAP Gross Margin | 36.7% | ~36.0% | +70bps |
| GAAP EPS | ($0.06) | Negative | -- |
| Non-GAAP EPS | $0.42 | -- | -- |
| Cash from Operations | $9.7B | -- | -- |
| Adjusted Free Cash Flow | ($1.6B) | -- | H2 was +$3.1B |
Revenue Trend (3-Year)
| Year | Revenue |
|---|---|
| 2022 | $63.1B |
| 2023 | $54.2B |
| 2024 | $53.1B |
| 2025 | $52.9B |
3-Year Revenue CAGR (2022-2025): -5.7%. Revenue has been shrinking for three years. The turnaround hasn't hit the top line yet.
Balance Sheet (End of FY2025)
| Item | Amount |
|---|---|
| Cash & Short-Term Investments | $37.4B |
| Total Debt | ~$44B |
| Net Debt | ~$6.6B |
| Stockholders' Equity | ~$100B |
| Book Value Per Share | ~$24.49 |
The balance sheet looks solid only because of massive external infusions (CHIPS Act, Nvidia, SoftBank, Altera sale). Without those, the picture is grimmer.
ROIC
- FY2025: approximately -0.01% (effectively breakeven)
- 3-year average: -0.43%
- Historical context: was 28% in 2020, collapsed to -14.2% in 2024
The business is not creating value for shareholders at present. The foundry segment is hemorrhaging money: ~$7B/year in losses at -50% operating margins.
Q1 2026 Guidance
- Revenue: $11.7B--$12.7B (disappointing)
- Non-GAAP EPS: $0.00 (breakeven)
- Company expects positive adjusted FCF for full-year 2026
Valuation
| Metric | Current | Notes |
|---|---|---|
| Forward P/E (2026E) | ~93x | Based on 2026E earnings |
| Forward P/E (2027E) | ~50x | -- |
| Trailing P/E | N/M | Negative GAAP earnings |
| EV/EBITDA | 22.6x | -- |
| P/FCF | N/M | Negative FCF in FY2025 |
| EV/Revenue (P/S) | ~4.1x | Peer avg is 9.7x |
| Price/Book | ~1.8x | Book value $24.49/share |
Intel looks "cheap" on P/S (4.1x vs semiconductor average of 9.7x) but that reflects the lower-margin business mix and negative earnings trajectory. On P/E, it's extremely expensive at ~93x 2026E and ~50x 2027E -- you're paying a high multiple for a business that is barely profitable and still losing money in its foundry.
Bull case on valuation: If 18A succeeds and Intel returns to $80B+ revenue with 40%+ gross margins by 2028--29, the stock could be worth $80--100+. At $43, you're getting a free option on that outcome with significant government backing limiting downside.
Bear case: If the turnaround fails, Intel could trade back toward book value ($24.49) or even lower as the foundry consumes cash. 44% downside to book. In a worst case (foundry abandoned, continued share loss), sub-$20 is possible.
Analyst Consensus
| Metric | Value |
|---|---|
| Consensus Rating | HOLD |
| Buy | 20% (9 of ~45 analysts) |
| Hold | 70% (33 analysts) |
| Sell | 10% (6 analysts) |
| Median Price Target | $48.00 |
| Average Price Target | $45.74--$48.21 |
| High Target | $71.50 |
| Low Target | $20.40 |
Implied upside from consensus: ~5--11% from $43.34. Not exactly a ringing endorsement.
Catalysts & Risks
Positive Catalysts
- CHIPS Act funding: $7.86B finalized under Biden; additional $8.9B under Trump administration with 5-year warrant at $20/share
- U.S. government equity stake: Commerce Department converted grants into 9.9% direct equity stake in Intel
- Strategic investments: SoftBank ($2B) + Nvidia ($5B) -- validation of foundry strategy
- Panther Lake shipping: First 18A product now in customer hands
- DCAI revenue surge: +32% YoY in FY2025 -- data center business recovering
- Cash position: $37.4B in cash/investments provides multi-year runway
- Altera divestiture: $4.3B from Silver Lake; simplifies the business
Key Risks
| Risk | Severity | Detail |
|---|---|---|
| 18A/14A Execution | HIGH | Yields won't reach standard levels until 2027; if external customers don't commit, foundry strategy fails. Process variation may structurally limit addressable foundry TAM. |
| Foundry Losses | HIGH | ~$7B annual losses; operating margins of -50%; massive cash drain |
| Market Share Erosion | HIGH | AMD approaching 30% server share; ARM alternatives growing |
| Capital Intensity | HIGH | Tens of billions needed for fabs with uncertain ROI |
| Negative ROIC | MEDIUM | Destroying shareholder value at current return levels |
| Cash Burn | MEDIUM | Negative FCF in FY2025; targeting breakeven in 2026 |
| AI Competitive Gap | MEDIUM | Nvidia/AMD dominate AI accelerators; Intel's Gaudi negligible |
| CHIPS Act Strings | MEDIUM | Must maintain 51%+ foundry ownership; limits strategic flexibility |
| Valuation Risk | MEDIUM | Stock at ~50x 2027E earnings; priced for turnaround success |
| Geopolitical/Regulatory | LOW-MED | U.S.-China tensions; potential trade disruptions |
Behavioral Traps to Watch
- FOMO -- Stock already up 209% from mid-2025 low. Some FOMO, but 20% pullback from high.
- Narrative seduction -- "National champion semiconductor turnaround backed by the U.S. government" is an incredibly compelling story. But the data doesn't support the narrative yet -- revenue flat, margins thin, foundry burning billions.
- Authority bias -- Lip-Bu Tan's Cadence track record, Nvidia's $5B investment, CHIPS Act backing all lend authority. But authority endorsements don't guarantee execution.
This is primarily a narrative-driven investment at this point. The financials don't yet support the stock price.
Decision Log
Pre-Buy Assessment (March 9, 2026)
Price: $43.34 | Recommendation: WATCH -- do not buy yet.
Scorecard:
| Dimension | Rating | Comment |
|---|---|---|
| Business Quality | C+ | Turnaround underway but unproven; still losing share |
| Financial Health | B- | Strong cash ($37.4B) offset by $44B debt and negative FCF |
| Valuation | C | Cheap on P/S vs peers, expensive on earnings (negative/breakeven) |
| Competitive Position | C | Weakened moat; foundry unproven; AI gap significant |
| Management | B+ | Tan is credible; aligned via equity; but early innings |
| Catalysts | B+ | CHIPS Act, Nvidia/SoftBank backing, 18A progress |
| Risk Profile | HIGH | Execution risk on every front; massive capital needs |
| Technical Setup | C- | Below both key MAs; correcting after big rally |
Technical snapshot (Mar 9, 2026):
| Indicator | Value | Signal |
|---|---|---|
| Price vs 50-day MA ($45.05) | Below | Bearish |
| Price vs 200-day MA ($47.21) | Below | Bearish |
| 14-Day RSI | ~47--51 | Neutral -- not oversold |
| Avg Daily Volume | ~85M shares | Highly liquid |
Stock crossed below 50-day MA on March 6 -- short-term bearish. Trading below both 50-day and 200-day MAs -- corrective phase. RSI neutral means further downside is possible.
Conviction level: Medium. The asymmetry is attractive but execution risk is severe.
Position sizing: 2--3% of portfolio max. This is a speculative turnaround with binary outcomes.
Entry strategy: Scale in. Start with 1% at $40--42 (near current levels, below both MAs). Add 1% on pullback to $35--38 (major support) or on a positive 18A yield update. Full 3% only after tangible foundry progress. Mental stop at $25 (near book value).
Bottom Line
Intel is the most asymmetric setup on this list -- if the turnaround works, the stock could double or triple. But the current financials are terrible (flat revenue, 0% ROIC, foundry hemorrhaging money), the valuation is steep at 93x forward earnings, and the stock just broke below both key moving averages. The government backing and Tan's credibility provide a floor, but execution risk is severe and multi-year.
The 18A process variation analysis from Discord insiders adds a critical nuance: even if Intel hits yield targets, the type of chips the foundry can competitively produce may be structurally limited. TSMC's real moat is consistency, not density. Intel may end up as a viable foundry only for large-die, binnable products (datacenter CPUs, AI accelerators) rather than the high-volume mobile and networking TAM that makes foundry economics work.
The disciplined approach: wait for either (a) a deeper pullback to the $35--38 range, or (b) a concrete positive catalyst (18A yield milestone, external foundry customer announcement). A 1% tracking position at $40--42 is acceptable for high-conviction turnaround investors, but don't size up until you see evidence that the turnaround is actually working.
Research Workflow
Near-term (next 3--6 months): Monitor Intel earnings calls for foundry language shifts. Watch for IEDM 2025 papers on 18A. Track Panther Lake preview benchmarks.
Medium-term (6--12 months): Panther Lake launch reviews -- look for power variance across samples. Any external customer announcements. Clearwater Forest server launch execution.
Ongoing: Discord/SemiWiki for insider chatter. EDA vendor commentary. Patent filing trends. IFS quarterly external revenue.
Topics
ai-infrastructure | supply-chain-security
Source updates (auto-maintained)
Beyond The Hype (Aug 27, 26) - Beyond The Hype - Looking Past Management & Wall Street Hype
The article covers Nvidia's Q2 FY27 earnings — Intel is mentioned only as a size benchmark ("each quarter, Nvidia is adding about an Intel or AMD worth of business") and as a future top-3 server CPU peer displaced by Nvidia's Vera CPU bundling strategy.
Relevant to your thesis: Nvidia's Vera CPU scaling into a top-3 server CPU supplier is a direct incremental bear signal for Intel's DCAI segment, where holding server market share is already a monitored exit criterion.
Source: https://enertuition.substack.com/p/nvidia-train-moves-again
Vik's Newsletter (Aug 24, 26) - Vik's Newsletter
SK Hynix's Hot Chips talk noted Intel's EMIB packaging is in active use, with a slide explicitly calling out "customers using their memory with Intel's packaging."
Relevant to your thesis: Directly supports the leading indicator "Google TPU v8e using EMIB advanced packaging in 2H27" — external memory players are already designing around Intel packaging, validating the packaging-as-easier-sell angle.
Source: https://www.viksnewsletter.com/p/hot-chips-2026-tuning-into-memory
Drop/Technology paper (Aug 27, 26) - HC2026.XCENA-Samsung.Kim.v02
The article benchmarks XCENA MX1 (Samsung Foundry 4nm) against an Intel Xeon 6767P baseline, showing near-memory compute delivering up to 4.7× throughput and 18.7× better energy efficiency for analytics kernels vs. running them over CXL on the host CPU.
Relevant to your thesis: Mild DCAI headwind — CXL-PNM architectures offload bandwidth-bound AI workloads away from the host Xeon, chipping at Intel's server CPU value proposition in exactly the inference segment it needs to grow.
Source: dropfile://Technology paper/Hot Chips 2026/HC2026.XCENA-Samsung.Kim.v02.pdf
Drop/Technology paper (Aug 27, 26) - HC2026.SK hynix.Jaesik_FINAL1
The article cites Intel's EMIB (Embedded Multi-die Interconnect Bridge) as a recognized advanced packaging architecture alongside TSMC's CoWoS family for HBM-on-interposer integration in AI accelerator systems.
Relevant to your thesis: Corroborates the wiki's note that Intel's packaging business may be the easier foundry sell — EMIB appears as an established industry option, not a fringe entrant, which supports the Google TPU v8e (2H27) packaging win as plausible.
Source: dropfile://Technology paper/Hot Chips 2026/HC2026.SK hynix.Jaesik_FINAL1.pdf
Drop/Technology paper (Aug 27, 26) - FINAL_Intel Crescent Island GPU Hot Chips 2026
Intel unveiled Crescent Island at Hot Chips 2026, a 32-Xe-core GPU built on the Xe3P architecture targeting agentic AI inference, featuring up to 480GB LPDDR5x, 350W air-cooled PCIe form factor, FP4–FP64 datatype support, and an open software stack (OneAPI/Triton/SYCL).
Relevant to your thesis: Crescent Island is a direct DCAI play — if it gains traction with enterprise inference workloads, it supports the +32% YoY DCAI growth trajectory and partially hedges Intel's GPU share gap against Nvidia's Gaudi narrative.
Source: dropfile://Technology paper/Hot Chips 2026/FINAL_Intel Crescent Island GPU Hot Chips 2026.pdf
Drop/Technology paper (Aug 27, 26) - FINAL_AMD Instinct MI400 GPU Architecture_HotChips (1)
The AMD MI400 Hot Chips paper references Intel only as a co-author on the OCP FP8 and OCP MX specification standards alongside Nvidia, ARM, Google, Meta, and others — no competitive commentary on Intel's foundry or CPU business.
Relevant to your thesis: Tangential — flagged for review.
Source: dropfile://Technology paper/Hot Chips 2026/FINAL_AMD Instinct MI400 GPU Architecture_HotChips (1).pdf
Drop/Technology paper (Aug 27, 26) - DMR at Hot Chips 2026_FINAL
Diamond Rapids (1H27) is Intel's next-generation Xeon built on 18A-P, featuring up to 256 cores, 1.28GB LLC, 1.6TB/s memory bandwidth, and a modular "Fan-out Fabric Architecture" using Foveros 3D Direct; Intel claims 18A-P delivers 33% tighter skew corners and improved process variation versus 18A.
Relevant to your thesis: The 33% tighter skew corners on 18A-P directly addresses the process variation bear case — Diamond Rapids is the first named product that will live or die on whether that improvement holds in production.
Source: dropfile://Technology paper/Hot Chips 2026/DMR at Hot Chips 2026_FINAL.pdf
Drop/Optics (Aug 25, 26) - An_800_Gbps_Fiber_Silicon_Photonic_Microring-Based_DWDM_Tran...
Intel researchers demonstrated an 800 Gbps/fiber silicon photonic DWDM transceiver using micro-ring resonators, built with Intel's 22nm CMOS EIC 3D-assembled with an Intel Fab11X photonic IC in an open-cavity package, achieving BER<1e-9 across 16 wavelengths simultaneously at 50 Gbps/λ.
Relevant to your thesis: Validates Intel's packaging and photonics capability as a real differentiator — consistent with the wiki's observation that Google TPU v8e's EMIB advanced packaging win may be an easier sell than front-end fab, and supports co-packaged optics as a potential foundry value-add beyond pure process node competition.
Source: dropfile://Optics/An_800_Gbps_Fiber_Silicon_Photonic_Microring-Based_DWDM_Transceiver_in_an_Open-Cavity_Package.pdf
Drop/Memory (Apr 21, 26) - Old Memory- Ongoing Asymmetric Risks_MS_26.04.19
Morgan Stanley (Apr 2026) flags Intel's EMIB-T as a new revenue vector for AP Memory silicon capacitors, noting industry concerns about Intel's ability to mass-produce EMIB-T products and serve external clients due to limited experience and yield/execution risk vs. TSMC.
Relevant to your thesis: Directly reinforces the bear case — external customers are actively discounting Intel Foundry's operational track record on EMIB-T, consistent with the "variation thesis" and the narrowing foundry TAM funnel detailed in the wiki.
Source: dropfile://Memory/Old Memory- Ongoing Asymmetric Risks_MS_26.04.19.pdf
Drop/Google Infra (Dec 30, 25) - Inside Google’s Ironwood TPU v7 Supply Chain - by Phabian
Intel is named as a BMC SoC supplier and OpenBMC contributor in the system integration and firmware layer of Ironwood TPU v7 racks, alongside Broadcom — a minor, non-core role.
Relevant to your thesis: Marginally bearish context — Intel's Ironwood presence is infrastructure glue (BMC firmware), not foundry silicon, consistent with the wiki's "captive + government" design-win concern and the narrow foundry TAM funnel thesis.
Source: dropfile://Google Infra/TPUs/Inside Google’s Ironwood TPU v7 Supply Chain - by Phabian.pdf
Drop/Google Infra (Dec 30, 25) - 3. TPU Mania - by Babbage (13 Dec 25)
The article notes that Intel's response to Google's TPU v1 was an acquisition spree (Nervana, Movidius, Mobileye, Habana), and that Intel Foundry is slated to manufacture Google TPU v8e via EMIB advanced packaging in 2H27 per the roadmap context in the wiki.
Relevant to your thesis: The Google TPU v8e EMIB packaging win (2H27) is a leading indicator already flagged in the wiki — this article's broader GPU vs. TPU framing reinforces that packaging may be an easier near-term revenue path than front-end fab wins.
Source: dropfile://Google Infra/TPUs/3. TPU Mania - by Babbage (13 Dec 25).pdf
Drop/Google Infra (Dec 30, 25) - 2. Chip Letter - Google's First Tensor Processing Unit - Arc...
Google's TPU v1 (2015) introduced a 256×256 systolic array running 8-bit integer matrix multiply on a PCIe-attached ASIC — an architecture Google described as launching "a thousand chips" in custom silicon.
Relevant to your thesis: Google TPU v8e is listed in the wiki roadmap as an Intel EMIB packaging customer in 2H27; this historical context shows Google's long-standing preference for custom silicon over merchant solutions, making the EMIB win meaningful if it holds.
Source: dropfile://Google Infra/TPUs/2. Chip Letter - Google's First Tensor Processing Unit - Architecture (Mar 24).pdf
Drop/Google Infra (Dec 30, 25) - 1. Chip Letter - Google's First Tensor Processing Unit _ Ori...
The article briefly cites Intel's 80170 analog neural network chip as an early example of dedicated AI hardware abandoned when the hype cycle turned, contrasting it with Google's TPUs as the first accelerators to be deployed at scale.
Relevant to your thesis: Historical backdrop for the wiki's Google TPU v8e / Intel EMIB packaging win (2H27) — Google's openness to non-Nvidia silicon has deep roots, but this 2024 article predates any Intel foundry relationship and adds no new signal.
Source: dropfile://Google Infra/TPUs/1. Chip Letter - Google's First Tensor Processing Unit _ Origins (Feb 24).pdf
Drop/Google Infra (Dec 21, 25) - SA_Google AI Infrastructure Supremacy_ Systems Matter More T...
Intel is named only as one of several AI hardware firms for brief comparison; Google's TPUs, co-developed with Broadcom, have been fabricated exclusively at TSMC across all six generations through TPUv5.
Relevant to your thesis: Confirms Google's foundry relationship sits firmly with TSMC — making the GFHK-sourced claim of Google TPU v8e on Intel EMIB packaging (2H27) an advanced-packaging play only, consistent with the wiki's note that "Intel's packaging business may be the easier sell than its front-end fab."
Source: dropfile://Google Infra/SA_Google AI Infrastructure Supremacy_ Systems Matter More Than Microarchitecture (Apr 23).pdf
Drop/GPUs (Dec 21, 25) - SA_ Deep Dive_GB200 Hardware Architecture - Component Supply...
The article covers Nvidia's GB200 rack architecture and component supply chain in detail; Intel appears only in passing as a comparison point (Intel Gaudi listed alongside AMD MI300X as competing AI accelerators) with no substantive coverage.
Relevant to your thesis: Tangential — flagged for review.
Source: dropfile://GPUs/SA_ Deep Dive_GB200 Hardware Architecture - Component Supply Chain & BOM.pdf
Beyond The Hype (Aug 5, 26) - Beyond The Hype - Looking Past Management & Wall Street Hype
AMD Q2'26 earnings showed data center revenue +107% YoY to $6.7B, server CPU revenue guided to grow >80% YoY in 2H26 and >70% for full-year 2027, with CEO Lisa Su projecting data center segment revenue to more than double YoY in 2027 as Venice EPYC gains traction and Helios MI450 ramps.
Relevant to your thesis: Directly feeds the INTC bear case — AMD's server CPU share is accelerating (">70% server growth in 2027"), with Venice claiming >2x performance-per-watt vs. Intel x86, reinforcing the wiki's "DCAI market share drops below 50%" exit trigger.
Source: https://enertuition.substack.com/p/amd-firing-on-all-cylinders-but-lisa
Beyond The Hype (Jul 22, 26) - Beyond The Hype - Looking Past Management & Wall Street Hype
AMD's upcoming Verano CPU is expected to "leave Intel and Nvidia CPU offerings in even more of a dust" in performance per watt, per BTH; AMD's EPYC is already approaching 30% server share with strong margin tailwinds.
Relevant to your thesis: Reinforces the bearish DCAI bear case — if AMD's server CPU leadership widens further with Verano, Intel's already-eroding data center share faces accelerating pressure, directly threatening the exit criterion of DCAI share holding above 50%.
Source: https://enertuition.substack.com/p/amd-anthropic-deal-and-advancing
Beyond The Hype (Jul 24, 26) - Beyond The Hype - Looking Past Management & Wall Street Hype
AMD's Advancing AI event revealed Venice CPU outperforming Nvidia Vera Rubin on per-core performance and throughput, with AMD claiming MI455 holds 30% TCO advantage on inference; Anthropic confirmed as AMD's largest 2027 customer with ~2GW MI450 order.
Relevant to your thesis: AMD's accelerating datacenter momentum and aggressive EPYC expansion directly pressures Intel's DCAI segment, reinforcing the bear trigger "AMD/ARM taking too much" server share that would break the thesis.
Source: https://enertuition.substack.com/p/strong-amd-advancing-ai-day-runs
Beyond The Hype (May 11, 26) - Beyond The Hype - Looking Past Management & Wall Street Hype
CC Wei commented that Intel's EMIB "looks good on paper" and expressed hope Intel could execute, as TSMC lacks capacity and Intel success would let TSMC focus on the more valuable silicon — he was unconcerned about losing foundry share to Intel.
Relevant to your thesis: TSMC's capacity constraints and CC Wei's neutral-to-welcoming stance on Intel EMIB supports the packaging-as-easier-entry-point thesis flagged under the 2H27 Google TPU EMIB win.
Source: https://enertuition.substack.com/p/tsmc-prospects-look-stronger-than
Drop/(root) (Jul 12, 26) - EP50. Breaking the 5kW GPU Power Supply Limit_ Analyzing Int...
Intel's EP50 article details its Integrated Voltage Regulator (IVR) and vertical power delivery (VPD) technology for AI accelerators, showing how advanced packaging moves voltage conversion directly beneath or within the chip package to cut I²R losses as GPU power approaches 5kW.
Relevant to your thesis: Intel's packaging capability (EMIB, IVR) represents a near-term moat that could attract foundry customers before front-end 18A yield issues are resolved — consistent with the GFHK roadmap's Google TPU v8e EMIB win in 2H27.
Source: dropfile://EP50. Breaking the 5kW GPU Power Supply Limit_ Analyzing Intel's Vertical Power Supply and IVR Development Roadmap - Ted Yu.pdf
Drop/Bottleneck (Jul 5, 26) - ASIA AI Semi Sever
Intel's EMIB-T (embedded multi-die interconnect bridge with TSV) is described as "potentially the biggest threat to TSMC's advanced packaging," prompting TSMC to accelerate its CoWoS roadmap and develop SoIC and CoPoS as countermeasures.
Relevant to your thesis: EMIB-T gaining credibility as a packaging threat to TSMC supports the bull case that Intel's advanced packaging business — not just front-end fab — could be an easier early win for external foundry customers, consistent with the Google TPU v8e EMIB signal in the roadmap section.
Source: dropfile://Bottleneck/ASIA AI Semi Sever.pdf
Drop/3. Backend (Mar 11, 26) - Rigaku Investment Thesis [Feb 13, 2026]
The Rigaku thesis highlights Intel's EMIB advanced packaging as a projected 2H27 customer win for Rigaku's X-ray inspection tools, validating that 3D packaging complexity creates structural inspection bottlenecks.
Relevant to your thesis: Corroborates the wiki's note that Intel's packaging business may be the easier foundry sell — external suppliers are already building around EMIB as a real revenue line.
Source: dropfile://3. Backend/OSAT-Test/Rigaku/Rigaku Investment Thesis [Feb 13, 2026].pdf
Drop/2. Frontend (Apr 21, 26) - Old Memory- Ongoing Asymmetric Risks_MS_26.04.19
Morgan Stanley (Apr 2026) flags Intel EMIB-T as a meaningful new revenue opportunity, noting AP Memory as the primary silicon capacitor supplier with ~$100 content per chip and 50%+ incremental revenue upside — while cautioning that Intel's lack of mass-production EMIB-T experience and external customer execution raises yield/operational risk vs. TSMC CoWoS.
Relevant to your thesis: Directly corroborates the Google TPU v8e EMIB win on the roadmap while adding a bear-side nuance — packaging may be easier to sell than front-end fab, but Intel's execution inexperience is a real risk flag.
Source: dropfile://2. Frontend/Memory/Old Memory- Ongoing Asymmetric Risks_MS_26.04.19.pdf
Drop/2. Frontend (Dec 30, 25) - 3. TPU Mania - by Babbage (13 Dec 25)
The article notes that TPU v1's 2015 debut triggered Intel's buying spree of ML chip companies (Nervana, Movidius, Mobileye, Habana), and that Google's TPU v8e is slated as an EMIB advanced-packaging customer for Intel Foundry in 2H27 per the GFHK roadmap context.
Relevant to your thesis: The Google TPU v8e EMIB win in 2H27 is a named leading indicator in the wiki — this article confirms Google's TPU program is scaling externally, making that packaging design win more strategically significant if it closes.
Source: dropfile://2. Frontend/Google Infra/TPUs/3. TPU Mania - by Babbage (13 Dec 25).pdf
Drop/2. Frontend (Dec 30, 25) - 2. Chip Letter - Google's First Tensor Processing Unit - Arc...
This article covers Google TPU v1's systolic array architecture for matrix multiplication, with no material content about Intel's business, process nodes, or foundry strategy.
Relevant to your thesis: Tangential — flagged for review.
Source: dropfile://2. Frontend/Google Infra/TPUs/2. Chip Letter - Google's First Tensor Processing Unit - Architecture (Mar 24).pdf
Drop/2. Frontend (Dec 30, 25) - 1. Chip Letter - Google's First Tensor Processing Unit _ Ori...
The article covers Google TPU's origins, noting Google is on the GFHK roadmap to use Intel's EMIB advanced packaging for TPU v8e in 2H27; the article itself predates that roadmap and focuses on why Google built its own accelerator rather than relying on Nvidia GPUs.
Relevant to your thesis: Confirms Google's long-standing appetite for custom silicon alternatives to Nvidia — consistent with the GFHK roadmap claim that Google TPU v8e will use Intel EMIB packaging in 2H27, which the wiki flags as an easier sell than Intel's front-end fab.
Source: dropfile://2. Frontend/Google Infra/TPUs/1. Chip Letter - Google's First Tensor Processing Unit _ Origins (Feb 24).pdf
Drop/2. Frontend (Dec 21, 25) - SA_Google AI Infrastructure Supremacy_ Systems Matter More T...
The April 2023 SemiAnalysis piece benchmarks Google's TPU infrastructure advantage over Microsoft, Amazon, and Meta, noting Intel's Gaudi accelerator is mentioned only in passing as a minor competitor with negligible presence in the AI training/inference stack. Relevant to your thesis: Reinforces the bear case — Intel's AI accelerator business (Gaudi) has no meaningful foothold in hyperscaler AI infrastructure, consistent with the wiki's assessment that Intel holds negligible AI accelerator share versus Nvidia.
Source: dropfile://2. Frontend/Google Infra/SA_Google AI Infrastructure Supremacy_ Systems Matter More Than Microarchitecture (Apr 23).pdf
Drop/2. Frontend (Dec 21, 25) - SA_ Deep Dive_GB200 Hardware Architecture - Component Supply...
The GB200 supply chain deep-dive covers Nvidia's rack architecture and component ecosystem extensively but contains no meaningful mention of Intel beyond listing "Intel Gaudi" once as a competing accelerator in passing.
Relevant to your thesis: Confirms Gaudi's peripheral status — grouped with AMD MI300X and AWS Trainium as alternatives to Nvidia's dominant GB200 ecosystem, reinforcing the bear case that Intel's AI accelerator franchise has negligible share.
Source: dropfile://2. Frontend/GPUs/SA_ Deep Dive_GB200 Hardware Architecture - Component Supply Chain & BOM.pdf
Drop/(root) (Jul 5, 26) - ASIA AI Semi Sever
Intel's EMIB-T (embedded multi-die interconnect bridge with TSV) is described as "potentially the biggest threat to TSMC's advanced packaging," prompting TSMC to accelerate SoIC and CoPoS roadmaps in response; separately, OSATs are flagged as beneficiaries of CPU-driven CoWoS-like full-process demand.
Relevant to your thesis: EMIB-T gaining external recognition as a competitive threat to TSMC packaging reinforces the bull case that Intel's advanced packaging business may be the easier foundry entry point than front-end fab — a leading indicator flagged in the wiki.
Source: dropfile://ASIA AI Semi Sever.pdf
Beyond The Hype (May 11, 26) - Beyond The Hype - Looking Past Management & Wall Street Hype
The article argues TSMC capacity is not as constrained as market narratives suggest, calling the view that "Intel gaining share at the expense of TSMC" a "particularly bad take."
Relevant to your thesis: Directly bearish on the "TSMC capacity crunch creates Intel foundry demand" narrative, reinforcing the wiki's foundry TAM funnel skepticism — external customers aren't being forced to Intel by supply scarcity.
Source: https://enertuition.substack.com/p/tsmc-update-ahead-of-june-numbers
Vik's Newsletter (May 6, 26) - Vik's Newsletter
Intel's EMIB advanced packaging is gaining real traction — AWS, Cisco, SpaceX, and Tesla are live customers; Google TPU v8e targets 2H27; CFO Zinsner raised external packaging revenue guidance from "a few hundred million" to "north of a billion dollars per customer"; and EMIB's rectangular-panel format gives it a structural size advantage over TSMC's CoWoS-L on round wafers.
Relevant to your thesis: Directly confirms the GFHK roadmap's Google TPU v8e EMIB win and supports the "packaging may be the easier sell than front-end fab" observation — bullish signal that external revenue is moving from test chips to production orders.
Source: https://www.viksnewsletter.com/p/battle-for-advanced-packaging-tsmc-intel-amkor
Vik's Newsletter (May 6, 26) - Vik's Newsletter
Apple confirmed Intel Foundry will manufacture chips for future iPhone SoCs, a major win that drove INTC up ~10%; Intel also hired SK Hynix veteran Seok-Hee Lee to lead advanced packaging.
Relevant to your thesis: The Apple smartphone SoC win directly validates the 2H28 GFHK roadmap entry and refutes the mobile PVT variation objection — the single most powerful external customer catalyst identified in the leading indicators.
Source: https://www.viksnewsletter.com/p/twic-amd-mext-200g-vcsels-intc
Intake (May 12, 26) - cu-wiring-resin-primer
The copper-wiring and resin sub-layer primer identifies Intel Foundry's substrate chemistry suppliers (ABF, MEC CZ-series, Mitsui MicroThin) as near-monopoly chokepoints that gate any advanced-packaging ramp — including Intel 18A's CoWoS-equivalent stack, with MEC publicly disclosing CZ-8101 qualification into chiplet packaging.
Relevant to your thesis: The near-monopoly chemistry suppliers and their 12–36 month qualification cycles are a supply-side constraint on how quickly Intel Foundry can ramp external customers, adding a layer of execution risk to the 2H27–2H28 Apple/Nvidia/Google tape-out windows in the GFHK roadmap.
Source: intakefile://cu-wiring-resin-primer.md
Drop/z Misc (Apr 2, 25) - Hyundai Motor Securities – Field Trip Report on Japanese and...
The Hyundai Motor Securities field trip report does not mention Intel or INTC substantively; the article covers TSMC, SK Hynix, HBM demand, and Asian semiconductor supply chains, with Intel appearing only in the metadata tag.
Relevant to your thesis: Tangential — flagged for review.
Source: dropfile://z Misc/Hyundai Motor Securities – Field Trip Report on Japanese and Taiwanese Companies.pdf
Drop/Technology paper (Dec 14, 24) - 1-1_Mon_Mii_2063
A TSMC keynote (Dec 2024) by EVP Yuh-Jier Mii outlines the industry's logic scaling roadmap through CFET and High-NA EUV, with TSMC's N2 node featuring nanosheet devices and backside power delivery already in the roadmap toward A16.
Relevant to your thesis: Confirms TSMC's 2nm/A16 process cadence against which Intel 18A/14A must compete — the tightness of TSMC's process corners (their real moat, per the wiki) is precisely what this scaling precision represents.
Source: dropfile://Technology paper/1-1_Mon_Mii_2063.pdf
Drop/Tariff (Mar 11, 25) - 250307_Allen_AI_Race
The article frames Intel as illustrating that Moore's Law continuity does not predict which company delivers performance gains, using Intel's struggles as a cautionary analogy for AI chip competition; it also identifies preventing Huawei/SMIC from providing a viable Chinese AI chip alternative as a top U.S. strategic priority, positioning Intel's foundry ambitions as geopolitically consequential.
Relevant to your thesis: Reinforces the geopolitical/CHIPS Act pillar — if Huawei/SMIC close the gap, the "only Western-allied cutting-edge fab" moat erodes, but near-term export control pressure sustains Intel's strategic value to the U.S. government.
Source: dropfile://Tariff/250307_Allen_AI_Race.pdf
Drop/Robotics (Mar 19, 25) - The_Humanoid_100_-_Mapping_the_Humanoid_Robot_Value_Chain
Morgan Stanley's Humanoid 100 includes Intel under "Semis (Fab)" in the Brain category, identifying it as a potential enabler in the humanoid robot value chain alongside compute and fabrication suppliers — though the report offers no Intel-specific detail or confirmed humanoid customer wins.
Relevant to your thesis: Inclusion as a fab enabler in a robotics TAM framed at $60tn is mild background support for the external foundry demand thesis, but adds nothing concrete to the customer pipeline or 18A yield debate.
Source: dropfile://Robotics/The_Humanoid_100_-_Mapping_the_Humanoid_Robot_Value_Chain.pdf
Drop/Robotics (Aug 9, 25) - SA - America Is Missing The New Labor Economy – Robotics Par...
SemiAnalysis argues China is on a path to dominate general-purpose robotics through manufacturing scale and iteration speed, warning that the West is "positioned backward," with the US trailing-edge semiconductor ecosystem facing collateral damage as Chinese robotics firms decouple from American components.
Relevant to your thesis: Reinforces the geopolitical forcing-function bull case — accelerating Chinese manufacturing dominance in robotics strengthens the argument for U.S. government pressure on domestic semiconductor self-sufficiency, which is the same logic underpinning Intel's CHIPS Act backing.
Source: dropfile://Robotics/SA - America Is Missing The New Labor Economy – Robotics Part 1 (11 Mar 25).pdf
Drop/Citrini Articles (Jun 13, 25) - Citriniresearch_Humanoid_Robot_Primer
Intel (INTC) is flagged as a compute-layer company in Citrini's humanoid robotics thematic primer, which frames the robotics supply chain as a secular growth story trading at cyclical trough — the specific Intel commentary falls in the truncated compute section (p.37).
Relevant to your thesis: Tangential DCAI upside — robotics compute is an incremental demand vector but immaterial to the foundry/18A thesis; monitor for any explicit commentary on Intel's edge compute or accelerator positioning in the full report.
Source: dropfile://Citrini Articles/Primers/Citriniresearch_Humanoid_Robot_Primer.pdf
Drop/Bubble (Oct 9, 25) - on-bubble-watch
Marks's memo flags Nvidia (one of the Magnificent Seven) as emblematic of potential bubble psychology — "no price too high" sentiment — but does not address Intel directly; Intel's absence from that cohort is the implicit signal.
Relevant to your thesis: Intel's turnaround framing as a contrarian, out-of-favor IDM is the structural opposite of bubble-driven concentration — if Marks's bubble diagnosis proves correct, capital rotation away from Magnificent Seven names could benefit unloved re-rating candidates like INTC.
Source: dropfile://Bubble/on-bubble-watch.pdf
Drop/BE (Short Case) (Mar 11, 26) - [Updated] Bloom Energy Investment Thesis - Not Investment Ad...
The article is a bull case for Bloom Energy (BE) as an AI datacenter power supplier and does not mention Intel in any substantive way.
Relevant to your thesis: Tangential — flagged for review.
Source: dropfile://BE (Short Case)/[Updated] Bloom Energy Investment Thesis - Not Investment Advice.pdf
Drop/BE (Short Case) (Mar 11, 26) - Bloom Energy Investment Thesis [Not investment advice]
The article is a Bloom Energy (BE) bull thesis; Intel appears only as a named customer reference ("Shesha Krishnapura, Intel IT"), suggesting Intel IT uses Bloom's energy servers on-premises.
Relevant to your thesis: Tangential — flagged for review.
Source: dropfile://BE (Short Case)/Bloom Energy Investment Thesis [Not investment advice].pdf
Drop/2. Frontend (Dec 30, 25) - Inside Google’s Ironwood TPU v7 Supply Chain - by Phabian
Intel ($INTC) appears as a BMC SoC supplier and OpenBMC contributor in Google's Ironwood TPU v7 rack management layer — a minor, non-foundry role alongside Broadcom in firmware and telemetry infrastructure.
Relevant to your thesis: Confirms Intel's presence in the Ironwood ecosystem is limited to management silicon, not front-end foundry work — consistent with the bearish signal that Intel foundry wins remain captive/government-adjacent rather than commercial AI.
Source: dropfile://2. Frontend/Google Infra/TPUs/Inside Google’s Ironwood TPU v7 Supply Chain - by Phabian.pdf
Beyond The Hype (May 11, 26) - Beyond The Hype - Looking Past Management & Wall Street Hype
Nvidia's Q1 FY27 revenues of $81.6B exceeded Intel's all-time peak yearly revenue of $79B (2021); Nvidia forecasts a $200B CPU TAM with ~$20B in Vera CPU revenues for FY27, framing CPUs as a growth market Nvidia now competes in directly.
Relevant to your thesis: Nvidia entering the CPU TAM with Vera is a new competitive pressure on Intel's DCAI segment — the growth engine that must hold share for the turnaround to work.
Source: https://enertuition.substack.com/p/nvidia-thesis-change