AI CAPEX / CBRS

CBRS — Cerebras Systems

WIKI stocksemiai-infraipo updated 2026-08-29

Thesis

Wafer-Scale Engine vendor that lost the training market and stumbled into ultra-fast inference as a saving niche. 2nd IPO attempt 2026 after a failed 2024 try. OpenAI signed as anchor customer Jan 2026, replacing ≥90% G42 revenue concentration. Hardware GM 43% (2025) is below the ≥55% threshold for healthy semis and is distorted by a 33.4M-share OpenAI warrant priced at $0.00001 strike — effectively bundled equity giveaways with each WSE sold. WSE-4 must deliver FP8 support, hybrid-bonded SRAM, and 5–10× WSE I/O bandwidth (for KV-cache offload) to justify the IPO valuation. Three WSE generations have failed to ship any of those upgrades, so execution risk is high.

Business Model

  • Revenue drivers: Wafer-Scale Engine (WSE) hardware sales + cloud and other services
  • Key customers: OpenAI (anchor since Jan 2026, MRA + warrant); G42 (≥90% of revenue 2024–2025); other hyperscale AI buyers TBD
  • Competitive moat: Cross-reticle stitching IP (TSMC co-developed); PVT (Process/Voltage/Temperature) calibration across an entire wafer; uniquely positioned for hybrid-bonded SRAM-on-logic stacking

Key Metrics

Metric 2025 2024 Trend
Hardware revenue $358.4M $212.0M +69%
Total revenue $510.0M $290.3M +76%
Hardware GM 43% 35% +800 bps
Loss from ops $(145.9)M $(101.4)M wider
Net income (loss) $237.8M $(481.6)M inflated by $390M "other income"
Net cash from ops $(10.0)M $452.0M turned negative
FCF n/a n/a

Catalysts

  • IPO pricing 2026 (2nd attempt; first failed Oct 2024)
  • WSE-4 spec disclosure — FP8/MX support, SRAM capacity, I/O bandwidth
  • OpenAI MRA delivery milestones (warrant tranches vest as 2 GW of inference capacity is bought)
  • Market cap $40B trigger (vests 5.57M warrant shares; signals re-rating)
  • KV-cache streaming I/O upgrade (would meaningfully expand serviceable model size)
  • Hybrid-bonded SRAM wafer announcement

Risks

  • Customer concentration shifting from G42 (≥90% historical) to OpenAI (anchor); single-customer dependency persists
  • OpenAI warrant dilution: 33.4M shares at $0.00001/share, vesting in tranches with delivery milestones
  • KV-cache pressure on 44 GB SRAM ceiling — long context is economically deadly
  • No FP8 support; weights stuck at BF16 (16-bit), doubling memory footprint vs peers
  • WSE I/O bottleneck (1.2 Tbps); 5–10× short of needed bandwidth for KV streaming
  • Three WSE generations have not addressed obvious flaws (cores too small, no FP8, weak I/O)
  • Reported 43% hardware GM is gamed by warrant equity bundled into product sales
  • Hyper-competitive AI chip market (Nvidia, Groq, custom hyperscaler ASICs); Groq tried to sell themselves early 2025 with no buyers — bearish signal for the fast-inference category
  • $146M operating loss in 2025; "net income" inflated by $390M of one-time other-income items

Valuation

  • IPO valuation TBD; warrant clauses imply management is targeting $40B+ market cap
  • IA's bottoms-up: WSE-3 rack ASP ~$297K, COGS ~$172K, GM 42% (matches S-1)
  • Sizing guide: small position only; IA buying $50K (~2.4% of his $2.1M trading book) as event-driven trade, not core hold

Research Sources

Source updates (auto-maintained)

Drop/Technology paper (Aug 27, 26) - HC2026.Cerebras.JPFricker.v03

Cerebras announced the CS-4, a three-WSE-3 Turbo rack system with 132 GB SRAM, 7.2 Tbit/s I/O bandwidth (6× CS-3), 750 PFLOPS AI compute, and up to 30× faster inference than GPU; GA is targeted for Q3 2026, with CS-5 projected for 2027.

Relevant to your thesis: The 7.2 Tbit/s I/O directly addresses the wiki's "WSE I/O bottleneck (1.2 Tbps); 5–10× short of needed bandwidth" bear point — CS-4 closes that gap on paper, though execution risk on GA delivery remains.

Source: dropfile://Technology paper/Hot Chips 2026/HC2026.Cerebras.JPFricker.v03.pdf

Beyond The Hype (Jul 24, 26) - Beyond The Hype - Looking Past Management & Wall Street Hype

AMD announced a partnership with Cerebras at its Advancing AI event, which AMD framed as its answer to Nvidia's Groq acquisition — plugging a product hole in AMD's portfolio for the premium low-latency token market; BTH expects AMD to develop an internal offering for this niche by MI500/MI600.

Relevant to your thesis: Adds a major OEM distribution channel and strategic validation, but AMD treating it as a gap-filler (not a permanent commitment) reinforces the bear case that Cerebras occupies a temporary niche until hyperscalers build their own solution.

Source: https://enertuition.substack.com/p/strong-amd-advancing-ai-day-runs

Beyond The Hype (Jul 28, 26) - Beyond The Hype - Looking Past Management & Wall Street Hype

Sanmina confirmed a Cerebras design win as an "incremental program" in its core business, describing CBRS as upside not previously accounted for in guidance, with scale expected to expand in coming quarters.

Relevant to your thesis: Adds a second major manufacturing relationship for WSE hardware — a mild positive for execution credibility, but does not address the FP8, I/O, or GM concerns driving the bear case.

Source: https://enertuition.substack.com/p/sanmina-calm-before-the-storm

Drop/2. Frontend (May 4, 26) - IA - Cerebras IPO Analysis (Cbrs)

Irrational Analysis's May 2026 report dubs Cerebras "the clown car that stumbled upon a gold mine," details WSE core architecture (48KB SRAM/core, no FP8), dismisses SwarmX/MemoryX and unstructured sparsity as useless, and sizes IA's own position at a $50K IPO YOLO trade.

Relevant to your thesis: Directly confirms the wiki's core bear points — no FP8, training market failure, I/O bottleneck — while the $50K sizing matches the "small position only, event-driven trade" framing exactly.

Source: dropfile://2. Frontend/CBRS/IA - Cerebras IPO Analysis (Cbrs).pdf

Drop/2. Frontend (May 5, 26) - Cbrs

Irrational Analysis's May 2026 deep-dive calls Cerebras "the clown car that stumbled upon a gold mine," confirms no FP8 support, flags SwarmX/MemoryX as useless training appliances, and values the author's own position at a $50K "YOLO" IPO trade.

Relevant to your thesis: Confirms the wiki's core bear points — no FP8, weak I/O, training market failure — while the $50K sizing matches the wiki's "small position only, event-driven trade" framing exactly.

Source: dropfile://2. Frontend/CBRS/Cbrs.pdf

Drop/Technology paper (Jul 23, 25) - Software_Co-design_for_the_First_Wafer-Scale_Processor_and_B...

Technical paper from Cerebras describing the WSE-1/CS-1 software co-design stack: the Cerebras Graph Compiler auto-maps TensorFlow/PyTorch graphs to 400K cores with sparsity harvesting (ReLU 90% sparse, up to 2.4× perf gain) and flexible model/data parallelism; WSE-2 (850K cores, TSMC 7nm) is teased at the close.

Relevant to your thesis: WSE-1 baseline (18 GB SRAM, TSMC 16nm) confirms the architectural lineage the wiki critiques — three generations of iteration on the same compiler-centric stack with no FP8, no I/O breakthrough.

Source: dropfile://Technology paper/Software_Co-design_for_the_First_Wafer-Scale_Processor_and_Beyond.pdf

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