sector sectorsemicapequipment updated 2026-05-30

Semiconductor Capital Equipment & Test

Overview / thesis

The one-line thesis

Test, inspection, and metrology is the under-owned, under-modeled layer of the AI hardware build-out. The market pays up for the chip designers (NVIDIA, AMD) and the front-end equipment giants (ASML, AMAT, Lam, KLA), but the same AI capex flows through to a fragmented set of test-and-inspection suppliers whose economics are improving structurally, not just cyclically. The recurring insight across every source: as chips get more three-dimensional, more stacked, and more expensive per assembly, the cost of shipping a bad die explodes — so the industry tests more, tests earlier, and tests harder. That is a quality story layered on top of a volume story, and it is what re-rates this segment.

Why it matters now — the structural inflection

For most of semiconductor history, test, burn-in, and metrology were back-office cost centers: necessary, unglamorous, tightly managed. Three converging forces moved them to the center of the AI hardware conversation:

The AI accelerator build-out is a quality story, not just a volume story. When you build a $3,500 AI inference server, you cannot afford early-life failures shipped to a hyperscaler data center. The follow-the-capex chain is explicit: NVIDIA $100B+ AI infra, Microsoft $80B, Meta $40B → SK Hynix / Samsung / Micron HBM ramp → test, burn-in, probe-card, and metrology orders downstream (with a 6-12 month lag on capital systems and a continuous replacement cycle on consumables).
HBM makes Known Good Die (KGD) non-optional. When you stack 8-16 memory dies vertically to build HBM3e/HBM4, any single bad die ruins the entire $30-50 assembly. The stack-yield math is the single most-cited driver across these sources: at 97% per-die yield, an 8-die stack yields ~78%; getting per-die yield to 99.5% raises stack yield to ~96% — a difference worth thousands of dollars per package. That math forces wafer-level burn-in, HBM probe cards (up to 150,000 pins, 3x standard DRAM), and X-ray inspection of micro-bumps/TSVs into every HBM production line at SK Hynix, Samsung, and Micron.
Advanced nodes and chiplets raise test intensity per die. As transistors scale below 5nm the gate dielectric is only a few atoms thick, so Time-Dependent Dielectric Breakdown (TDDB) rises and burn-in intensity rises with it. GAA nanosheets (3nm/2nm), 200-300+ layer 3D NAND, and chiplet disaggregation (Intel 18A, AMD CDNA4) each increase metrology spend per wafer step and multiply the number of unique probe-card / KGD-certification designs per product. Intel's 18A re-entry, with glass-core substrates and EMIB-T packaging, is a recurring medium-term catalyst across the burn-in, probe-card, substrate, and metrology sources.

The cross-cutting "so what": the highest-growth segment of semiconductors (AI/HBM) is also the segment with the highest test intensity, and that intensity compounds with both wafer volume AND design complexity. The test layer captures the AI build-out twice — once on volume, once on the rising number of test insertions per device.

The single most important structural attribute — consumables

The recurring investment edge across the burn-in, probe-card, and socket sources is that the highest-quality revenue in this sector is consumable, not capital equipment:

Probe cards are consumed in production — each new device design, design revision, or technology shrink needs a new set, and cards wear out after millions of touchdowns. A single fab may run hundreds of different probe-card designs simultaneously. Revenue compounds with wafer volume AND design diversity — a powerful tailwind as the industry fragments into more chiplet and HBM variants.
WaferPak / DiePak consumables (Aehr's full-wafer contact interface, ~$80K-180K each, 30K-50K contact life) scale directly with HBM wafer volume. This is repeatedly flagged as the under-modeled, under-priced compounding leg: at ~$120K per WaferPak and high-volume DRAM throughput, a single major customer could imply $2M+/month; the open question is whether SK Hynix running 500+ HBM wafer-starts/day implies a $200-400M/year WaferPak TAM by 2027 that most models do not break out.
Test sockets and burn-in boards (BIBs) are design-locked and wear with use; every new HBM package generation and every AI-chip pin-count increase requires new socket/BIB designs (Yamaichi, KES Systems).

By contrast, X-ray metrology is capital equipment (lasts years, revenue tied to fab construction + node transitions) but throws off 20-30% of instrument price per year in recurring service/parts/consumables (X-ray tubes) once installed. The general principle the sources converge on: consumed products generate more predictable, recurring demand than capital goods — which is why Soitec (wafers consumed) is framed as more durable than Aixtron (machines last years), and why probe cards/WaferPaks are framed as better businesses than the ATE boxes they plug into.

Sizing the opportunity — segment TAM build

The test/inspection/metrology stack is roughly a $25-35B+ aggregate across its sub-markets, with the highest growth concentrated in the AI/HBM-exposed niches. Money-flow framing from the supply-chain source:

Sub-market	Approx. market size	Growth profile
Semiconductor metrology & inspection (total)	~$9-15B (estimates vary by source)	5-7% CAGR through 2033
ATE testers (Advantest, Teradyne)	~$6-7B	Capital cycle; AI-test spend surged ~48% in 2025
Probe cards	~$2.1-2.6B (2024) → $3.3-4.2B by 2030-2032	6-10% CAGR (HBM-amplified)
Wafer probers (TEL, Tokyo Seimitsu)	~$1-2B	Capital cycle
Handlers & test sockets (Cohu, Yamaichi)	~$1-2B	Final-test cycle
Wafer-level + package burn-in (total)	~$1.2-1.7B (2024E) → $2.4-3.7B (2028E)	~20-25% CAGR
X-ray analytical instruments (all end markets)	~$2.2-2.5B	3-5% CAGR (semi sub-segment far faster)

Burn-in TAM build (the fastest-growing slice):

Segment	2024E TAM	2028E TAM	CAGR
Wafer-level burn-in (systems + WaferPaks)	~$500-700M	~$1.5-2.5B	30-40%
Package-level burn-in (ovens + BIBs)	~$400-600M	~$500-700M	5-8%
Burn-in sockets / consumables	~$250-400M	~$350-550M	8-12%
Total	~$1.2-1.7B	~$2.4-3.7B	~20-25%

At peak HBM penetration, WLBI TAM alone could exceed $2B. The X-ray semiconductor metrology sub-segment ($300-500M today) is growing 15-25% CAGR — far outpacing the broader ~$2.2-2.5B X-ray analytical instruments market (3-5%) — with Rigaku's semiconductor process-control segment alone posting ~20% revenue growth in FY2025.

Demand anchors cited repeatedly: the HBM market is projected at $54.6B in 2026 (+58% YoY) with ~600% cumulative growth to 2030; Samsung and SK Hynix shipped >250M HBM stacks in 2025; SK Hynix has already sold out its entire 2026 HBM supply; CoWoS capacity remains sold out through 2026; HBM stacks are progressing 8-high → 12-high → 16-high, multiplying the TSV connections to test. Adjacent fab build-out (TSMC Arizona, Samsung Taylor, Intel Ohio, Rapidus/Japan's JPY 2T allocation, European Chips Act) adds a regionalization tailwind and, in Japan's case, domestic-sourcing mandates that benefit JEM and MJC.

The market-structure spread — concentration is the alpha map

A defining feature the sources surface: market structure varies dramatically across the test stack, and that variation is where positioning edge lives.

Near-monopoly / monopoly: Aehr in 300mm wafer-level burn-in and its captive WaferPak consumable (non-bypassable; the WaferPak stream is repeatedly flagged as under-priced); Lasertec in EUV mask inspection; Soitec at 70%+ of the SOI wafer market; Dexerials at 74% ACF / 93% anti-reflection films; Aixtron at 77% MOCVD share.
Duopoly / oligopoly: ATE (Advantest ~55-60%, Teradyne ~30%); semiconductor X-ray metrology (Rigaku vs. Bruker, with Malvern Panalytical entering); the top-3 XRD players hold >60% globally.
Fragmented (the exception): probe cards — 5+ meaningful players (FormFactor ~30%, Technoprobe ~15-18%, MJC ~14%, JEM ~5-7%, MPI ~5-7%; top 5 ≈ 73%). Probe cards resist consolidation because every chip design needs a unique card, qualification is customer-specific, regional preferences persist (Japanese IDMs → JEM/MJC; Korean memory → Korea Instrument/TSE), and technologies segment (cantilever vs. vertical vs. MEMS). No single firm can dominate the way ASML dominates litho — but the best-positioned players in the fastest-growing niche (HBM MEMS) capture outsized growth.

The investable implication the sources draw: in the consolidated layers, the bottleneck pure-plays (Aehr's WaferPak, Lasertec) are the cleanest exposures; in the fragmented probe-card layer, technology transition (cantilever → MEMS) decides winners and losers.

Barriers to entry — why the moats hold

The same moat structure recurs across burn-in, probe cards, and X-ray metrology and underwrites the durability of the thesis:

12-24 month qualification cycles at each customer (tool-of-record qualification, correlation studies, fab-automation integration, reliability demonstration). Fabs are extremely conservative about changing qualified test/metrology tools once installed.
Switching costs that compound with installed base — recipe migration (hundreds of measurement recipes), data continuity, retraining, and yield-loss risk worth millions per error.
Deep IP and domain expertise — MEMS contact technology (Aehr's 25+ years; Technoprobe/FormFactor MEMS fabrication requiring semiconductor-grade cleanrooms), X-ray source/optics/detector know-how (Rigaku 70+ years), thermal management for ±1-2°C uniformity at 175°C across 300mm wafers.
Recurring service/consumable tails that fund the next R&D cycle and reinforce the lead.

The key debates

What separates the durable thesis from the noise, per the sources:

Is it secular or just cyclical? Semiconductor test/metrology spend runs in 2-3 year boom/bust cycles (the probe-card market fell ~18% in 2023, rebounded sharply in 2024-25). The bull view is that HBM/AI demand is structural enough to dampen — not eliminate — the cycle: WLBI follows the HBM capex cycle (secular) more than the commodity DRAM/NAND cycle. The bear view is that these are still semi-cap names and a single AI-capex air-pocket re-rates the whole group.
Valuation has already run. Across nearly every comparison the sources flag that the easy entry is gone — the AI test/inspection complex has broadly re-rated (ATS.VI +426%, UCTT +362%, AWX +409%, Santec/JEM +237%/+246% over 52 weeks; many names at RSI >70-80, near 52-week highs). The live debate is which names are earnings-driven re-ratings with remaining runway (ATS.VI, ONTO) versus multiple-driven moves priced for perfection (UCTT ~65% multiple-driven, Aixtron at 30x+ EV/EBITDA, Santec at 38x P/E / RSI ~98).
The competitive-entry risks that would break specific moats. The most-cited single-name risks: Advantest developing a credible wafer-level burn-in product and qualifying it at Samsung (the most serious threat to Aehr, no timeline confirmed); KLA encroaching on advanced-packaging inspection from its optical-OCD dominance (the Onto risk); JEM failing to transition from cantilever to MEMS as the market moves to finer pitch/higher pin count; and Chinese domestic entrants (Hangzhou Changchuan in burn-in; MaxOne, Shanghai Zenfocus, JUNR in probe cards at ~2% share) capturing the commodity tier while remaining unable to serve HBM-grade applications near-term.
Geopolitics / export controls. US/Dutch/Japanese export controls already cover metrology tools and have constrained FormFactor's China probe-card shipments. Burn-in equipment is not yet restricted (a flagged but non-near-term risk). The same controls that limit China TAM for Western suppliers also seed long-term domestic competitors.

How the stages fit together (industry value chain)

The test-and-inspection flow is distinct from the manufacturing flow (litho/deposition/etch) — it verifies that what was built actually works, across five-plus stages: (1) in-line metrology & inspection during fab — optical (KLA, Onto), X-ray (Rigaku, Bruker), e-beam (AMAT, ASML/HMI); (2) wafer probe / wafer sort (CP test) — ATE + probe card + prober; (2.5) wafer-level burn-in for HBM/advanced packaging (Aehr); (3) dicing & packaging (DISCO, OSATs, TSMC CoWoS); (4) final test — ATE + socket + handler (Yamaichi, Cohu); (5) system-level test (SLT), growing because AI chips are too complex for traditional test alone. Each AI/HBM dollar touches multiple stages, and the steps reinforce one another — burn-in accelerates probe-card wear, driving incremental replacement demand; advanced packaging adds new KGD insertions and new metrology steps.

Company-specific detail

Industry-wide framing only here. Single-name theses, financials, and valuations live on the ticker and comparison pages: AEHR, 6855 (JEM), 268A (Rigaku), FORM, ONTO, ATS, UCTT, PDFS, AWX (AEM), S71 (Sunright), SOI (Soitec), AIXA (Aixtron), and the supporting primers burn-in-test-primer, semi-probe-card-primer, xray-semi-metrology-primer, semi-test-supply-chain.

How it works

The semiconductor capital-equipment-and-test sector is not one technology. It is a chain of physically distinct measurement, contact, and stress steps that each verify, or enable the verification of, a chip between the moment silicon comes off a fab line and the moment it ships. The unifying economic logic is simple and brutal: as packaging gets more expensive and dies get stacked, the cost of shipping a bad die — or assembling a known-bad die into a multi-thousand-dollar package — rises faster than the cost of testing it. Every theme below is a different physical answer to that same economic question. The test supply chain is distinct from the manufacturing supply chain (lithography, deposition, etch); it verifies that what was manufactured actually works.

The end-to-end flow: where each step physically sits

A chip passes through a fixed sequence of test and inspection insertions. Understanding the sector requires knowing what each step touches and why it cannot be skipped:

In-line metrology and inspection (Stage 1) — runs during fabrication, between process steps, on the production wafer. Verifies films, dimensions, defects, and contamination in real time. Three physical modalities: optical (KLA, Onto, Lasertec, Nova), X-ray (Rigaku/268A, Bruker), and e-beam (Applied Materials PROVision, ASML/HMI). Tools are connected to the fab's Manufacturing Execution System (MES) for closed-loop process control.
Wafer probe / wafer sort, "CP test" (Stage 2) — the first electrical test, performed after fab and before dicing, on every die while still on the wafer. Three subsystems work together: the ATE tester (Advantest ~55-60%, Teradyne ~30%), the probe card (the consumable contact interface — FormFactor, Technoprobe, MJC, JEM, MPI), and the wafer prober (the capital tool that holds and aligns the wafer — Tokyo Electron, Tokyo Seimitsu).
Wafer-level burn-in (Stage 2.5) — stress testing at elevated temperature and voltage to weed out early-life failures before the die is committed to an expensive stack. Aehr (AEHR) FOX-XP dominates; probe cards are used in the burn-in process, so burn-in accelerates probe card wear.
Dicing and packaging (Stage 3) — cut the wafer into dies, then package. DISCO (dicing), ASE/Amkor (OSAT), TSMC CoWoS, Samsung/SK Hynix HBM stacking in-house. For HBM, dies are stacked 8-12 high with TSV interconnects; for AI chips, chiplets are assembled on a CoWoS interposer.
Final test, "FT" (Stage 4) — test the packaged chip for speed, power, and function. Three subsystems: ATE tester, test socket (the consumable contact — Yamaichi/6941, 3M/Textool, Sensata, Ironwood), and handler (the capital tool — Advantest, Cohu, Teradyne).
System-level test, "SLT" (Stage 5) — run the chip in conditions mimicking real-world use, catching defects that wafer probe and final test miss. Growing because AI chips are too complex for traditional test alone. SLT supplements wafer probe; it does not replace it.

The economic distinction that runs through the whole chain: capital equipment (ATE testers, probers, handlers, metrology tools, burn-in ovens/systems) is bought once per fab line and lasts 5-10 years — lumpy revenue tied to fab construction. Consumables (probe cards, test sockets, burn-in boards, WaferPaks) are consumed in production, replaced every few months to a year, and scale with both wafer volume and design complexity. The consumable lines are the structurally attractive revenue pools because they compound continuously rather than arriving in capex bursts.

Known Good Die (KGD): the economic spine of the entire sector

The single concept that makes test economically non-optional at advanced nodes is Known Good Die — certifying that every die entering a high-value assembly has been verified functional. Packaging is expensive, especially at advanced nodes with 2.5D/3D stacking. For multi-die packages (chiplets, HBM stacks, SiP), a single bad die can scrap an entire assembly costing hundreds or thousands of dollars. Verifying KGD before assembly improves final package yield by more than 10% and prevents prohibitively expensive rework.

The HBM stack-yield arithmetic is the cleanest illustration: at 97% per-die yield, an 8-die stack yields only ~78%. Raising per-die yield to 99.5% through burn-in lifts stack yield to ~96% — a difference worth thousands of dollars per package. With each HBM stack worth $20-40+ (and full HBM assemblies far more), packaging a bad die is the most expensive mistake in the flow. Every die layer must be a verified KGD before stacking. This is why both probe (electrical screen) and burn-in (reliability screen) become mandatory, not optional, as stacking proliferates.

Burn-in: accelerating infant mortality before the customer finds it

The problem. Every fab process produces a distribution of devices. Most are fine; a small fraction carry latent defects — voids in metal interconnects, trapped contaminants at gate interfaces, micro-cracks in dielectric films — that are not immediately fatal but cause early-life failure under operating conditions. These cannot be caught by standard electrical test because the defect has not yet manifested. The chip passes every functional test, then fails three months into a server rack. Burn-in artificially accelerates the infant-mortality phase: subject the device to elevated temperature, elevated voltage, or both, for a controlled period; defective devices fail during burn-in; survivors emerge with statistically lower early-life failure probability.

The physics — Arrhenius acceleration. The entire economic basis of burn-in is the Arrhenius relation for reaction rates:

k = A × e^(-Ea / kT)

where k = failure rate, Ea = activation energy (eV), k = Boltzmann's constant, T = temperature (Kelvin). For typical semiconductor failure modes, activation energies range from 0.3 eV (electromigration) to 1.0 eV (time-dependent dielectric breakdown). A device operated at 125°C ages roughly 10-100× faster than at 25°C. That compression — weeks of normal aging into hours of stressed aging — is what makes burn-in pay.

Voltage acceleration. Higher voltage stresses gate dielectrics, raises current density (accelerating electromigration), and enhances hot carrier injection. JEDEC JESD-35 defines the voltage acceleration models. Most burn-in runs at 1.1-1.3× nominal supply voltage.

The bathtub curve. Failure rate over time is high during infant mortality, low through useful life, then rises again at wear-out. Burn-in moves devices through the infant-mortality region artificially before customer delivery.

Failure modes screened:

Time-Dependent Dielectric Breakdown (TDDB) — gate-oxide defects causing catastrophic insulation failure. As transistors scale below 5 nm, the gate dielectric is only a few atoms thick; any trapped charge or interface defect accelerates breakdown. TDDB is the dominant concern at 3 nm/2 nm and the reason burn-in intensity rises with each node advance.
Electromigration (EM) — metal atoms migrate along current paths, creating voids (open) or hillocks (short). Ea = 0.5-0.9 eV; strong thermal acceleration.
Hot Carrier Injection (HCI) — high-energy electrons injected into gate oxide, shifting threshold voltage and degrading transconductance. High-voltage burn-in screens this effectively.
Stress Migration (SM) — stress-driven atomic movement in metal interconnects from temperature cycling.
Soft Breakdown — partial dielectric failure that increases leakage without immediate catastrophic failure; devices degrade in operation.

Package-level process. Load packaged devices into sockets on burn-in boards (BIBs, 16-64 per board) → load BIBs into a burn-in oven (50-200 boards per oven; thousands of devices) → ramp to 105-130°C and apply 1.1-1.3× Vnom → hold 8-168 hours, static or dynamic → unload, re-test on final test, discard failures → ship survivors. Oven economics: $200K-$1M per oven (TESEC ovens $500K-$1.5M); cost per device $0.05-$0.50 depending on duration and yield.

Wafer-level burn-in (WLBI) — the HBM KGD flow. Wafer fab complete → wafer-level probe (CP test, basic sort) → wafer-level burn-in (Aehr FOX-XP: 125°C, 1.1-1.3× Vnom, 8-48 hours, dynamic pattern cycling through memory addresses, fail bins mapped at wafer level) → post-burn-in CP test, die sort and ink-mark → dicing → HBM stack assembly (TSV bonding) → HBM module test → CoWoS assembly → final system test. WLBI is in the critical path of every HBM production line at SK Hynix, Samsung, and Micron.

SiC power-device burn-in — a captive 100% market. Silicon carbide has a high density of basal-plane dislocations that cause "bipolar degradation" under forward current — a failure mode unique to SiC versus silicon. Automotive (ASIL-D) and industrial applications demand 0 DPM (defects per million), which mandates 100% wafer-level burn-in of every SiC device before packaging. Conditions: forward current at 175°C+, tens of thousands of switching cycles. Tesla's Model 3 SiC inverter (STMicro) drove Aehr's initial FOX-XP ramp.

Static vs. dynamic. Static burn-in holds fixed inputs at stress; screens TDDB and EM; cheap; misses logic-path defects. Dynamic burn-in runs functional vectors during stress; broader coverage; standard for complex logic. SLT is effectively dynamic burn-in plus system context.

Key burn-in metrics:

Metric	Package-Level	Wafer-Level (Aehr FOX-XP)
Throughput	3,200 devices/cycle (100 boards × 32 dev)	10,800+ dies/cycle (18 wafers × 600 dies)
Cycle time	8-168 hr	8-48 hr
Temperature uniformity	±3-5°C	±1-2°C (critical for HBM)
Contact life (consumables)	25K-50K insertions (socket)	30K-50K contacts (WaferPak)
Cost per device	$0.05-$0.50	$0.02-$0.15 (high-die-count wafers)

Package-level vs. wafer-level economics: package-level happens after packaging, is not KGD-capable, runs $200K-$1M per oven (declining for advanced applications), key vendors TESEC/Sunright/Chroma. Wafer-level happens before dicing, is KGD-capable, achieves full-wafer parallelism, runs $3-5M per system, vendor Aehr (dominant), and is rapidly growing on HBM.

The physics-derived moat (WLBI). Four reinforcing barriers: (1) MEMS contact technology — Aehr has 25+ years of development; no competitor has replicated full-wafer contact at scale for 300 mm; (2) thermal management for ±1-2°C uniformity at 175°C across a 300 mm wafer; (3) 12-18 month qualification cycles at each customer; (4) yield-correlation data requiring hundreds of thousands of devices. Package-level burn-in, by contrast, has low barriers — multiple Asian manufacturers compete on price.

The WaferPak consumable. Aehr's full-wafer contact interface is the captive, compounding economic engine: $80K-$180K per unit (~$120K typical), 30K-50K contacts, customer-specific design so no substitution without requalification. At ~$120K per WaferPak and 30K contact life, high-volume DRAM fab throughput implies $2M+/month per major customer. The system order is the lumpy, modeled leg; the WaferPak replacement stream is the under-priced, continuously compounding leg that arrives 12-18 months after system installation. DiePak extends the same physics to individual bare-die burn-in for chiplet pre-assembly KGD.

SLT and thermal handling: getting 2,000W of heat off an AI die

System-level test and burn-in both run hot, and modern AI accelerators dump enormous thermal loads. AEM's PiXL Active Thermal Control (ATC) platform handles heat loads above 2,000W per package — a requirement for AI accelerators and large CPU packages that commodity handlers cannot meet. The moat here is thermal IP (PiXL, ~40 patents) plus a 40,000+ unit Intel SLT installed base creating switching cost. The economics of the handler/SLT model are lumpy capital equipment with a recurring services-and-consumables tail; when the cycle works, ROIC reaches 33-51%. On the services side, fee-for-service burn-in is smoother but thinner — a high reported gross margin (e.g., 87%) can be a cost-classification artifact where ~80% of revenue is effectively operating cost below the gross line, so the operating outcome is binary around a revenue-inflection threshold (fixed cost base ~S$65-70M/yr). Burn-in board (BIB) requalification takes 3-6 months, which is enough friction to retain service customers through a cycle. Intel 18A is the most complex node Intel has attempted, and test intensity per die is higher.

Probe cards: the microscopic electromechanical interface to the wafer

What wafer probing is. Three sub-steps: Wafer Parametric Test (WPT) confirms the fab process ran correctly at a few sites; Wafer Functional Test / Die Sort tests every individual die and compiles a wafer map marking each die good or bad; inking/mapping flags bad dies so they never reach packaging.

How a probe card physically works. A probe card is a specialized PCB fitted with an array of microscopic contact elements (probes/needles). It sits between the wafer and the ATE: ATE (tester) → test head → probe card → wafer on prober chuck. The wafer prober vacuum-mounts the wafer, uses cameras to optically align probe tips to die pads, then raises the chuck to bring wafer pads into contact with the probes. Electrical signals flow through the probes to the ATE, which runs test programs and records pass/fail.

Three probe-card technologies:

Feature	Cantilever	Vertical	MEMS
Probe orientation	Horizontal — needles extend inward like wheel spokes	Perpendicular to wafer	Microfabricated springs, perpendicular
Pad pitch	Coarse (>100 µm)	Fine (60-100 µm)	Ultra-fine (<50 µm possible)
Pin count	Low-moderate	Moderate-high	Very high (up to 200K+)
Touchdown lifetime	500K - 2M	Up to 5M	10M+
Pad damage	Higher (lateral scrub)	Lower (vertical, no scrub)	Lowest (controlled force)
Planarity	Moderate	Good	Excellent (<±12.5 µm)
Cost	Lowest	Moderate	Highest upfront, lowest TCO
Primary application	Analog, legacy logic, driver ICs	Advanced logic, RF, GPUs	Leading-edge logic, DRAM, HBM, advanced packaging
Key players	JEM (strong here)	FormFactor, MPI	FormFactor, Technoprobe, MJC

Cantilever is the oldest — fine metal needles around the periphery, good for larger pads and lower pin counts. Vertical mounts probes perpendicular for denser arrays, smaller probe marks, reduced pad damage; the workhorse for mainstream logic and memory. MEMS uses semiconductor lithographic processes to fabricate micro-springs with sub-micron precision — best planarity, highest pin counts, longest lifetimes, lowest contact-resistance variation, but the most sophisticated manufacturing. MEMS is increasingly required at the leading edge.

Logic vs. memory vs. HBM cards. Logic/foundry: moderate pin counts (thousands to tens of thousands), mixed-signal (digital/analog/RF/I/O), high per-design customization, -40°C to 150°C range. DRAM: very high pin counts (>50,000), full-wafer contact (every die in one touchdown), repetitive regular pad arrays, speed testing up to 3.2 GHz / 6.4 Gbps for next-gen, MEMS-dominated. NAND: 30,000-50,000 pins, full-wafer contact, electrically less complex than DRAM.

Why HBM probe cards are the hardest engineering problem in the segment:

Massive parallelism — the industry is moving to single-touchdown full-wafer testing; HBM's 3× pin count vs. standard DRAM means achieving planarity across 150K+ probes simultaneously is an extreme mechanical challenge.
Extreme pin counts — up to 150,000 pins (3× standard DRAM), contacting ~4,000 micro-bumps per die at 45-55 µm pitch and 25 µm bump diameter.
Current density — probes thinner than a human hair must each carry >1A of current.
Thermal management — stacked DRAM layers generate intense localized heat requiring sophisticated thermal control.
Signal integrity — multi-GHz testing (beyond 4 GHz) across 150K channels requires controlled impedance, minimal crosstalk, low insertion loss.
CTE mismatch — different thermal expansion rates between the probe-card PCB and the silicon wafer cause alignment drift during thermal cycling, critical when targeting 25 µm bumps. Layer counts are climbing 8-high → 12-high → 16-high, multiplying TSV connections to test.

Key probe-card specifications:

Specification	Typical Range	Leading Edge
Pitch	80-200 µm	40-55 µm (HBM), <50 µm (MEMS)
Pin count	5,000-50,000	150,000+ (HBM), 200,000+ (MEMS capable)
Contact force	0.5-15 g per probe	Lower is better
Planarity	<25 µm variation	<±12.5 µm (high pin count)
Temperature range	Room temp	-40°C to 150°C
Touchdown lifetime	500K (cantilever)	10M+ (MEMS)
Contact resistance	<1 ohm target	Increases with wear

Wear physics and the consumable economics. Lifetime degrades through contact-resistance drift (tips wear with repeated touchdowns), contamination buildup (requires abrasive cleaning, which itself removes tip material), mechanical deformation (even slight distortion renders a card unusable), and technology transitions (new designs require entirely new cards — NRE). At advanced nodes, contact current density exceeding 15 mA/µm² can halve probe-tip lifetimes relative to 7 nm. Probe cards are consumables, not capital equipment: a manufacturer needs a new card for each new device design and each shrink; a single fab runs hundreds of different probe-card designs simultaneously. Revenue compounds with wafer volume and design complexity/diversity — a powerful tailwind as the industry fragments into more chiplet designs and HBM variants.

Pricing. Standard DRAM probe card $200-300K (200-300M KRW); HBM cards command a premium for 3× pin count, tighter pitch, and thermal complexity, estimated $500K-$1M+; leading-edge logic cards >$2.5M each (covering prototyping, material science, multi-temperature validation) — only the largest fabs can amortize this. ASPs are rising structurally; MEMS cards cost more upfront but lower TCO via longer life. Turnaround from design to delivery: 4-12 weeks standard, longer for leading-edge.

Material science as moat. Probe-tip materials (tungsten, palladium alloys, rhodium) must balance conductivity, hardness, wear resistance, and contact-resistance stability. MEMS fabrication requires semiconductor-grade cleanroom facilities, lithographic expertise, sub-micron machining, rhodium alloys, and AI-driven alignment algorithms — capex unlikely for new entrants. MPI's ultrasonic self-cleaning tip technology extends life ~50%, which lowers replacement frequency (a unit-volume headwind even as ASPs rise).

Why the probe-card market is uniquely fragmented. Unlike lithography (ASML monopoly) or ATE (Advantest/Teradyne duopoly), probe cards have 5+ meaningful players because: every device design needs a unique card (no standardization); customer-specific qualification creates high but not insurmountable switching costs; regional preferences (Japanese IDMs → MJC/JEM, Korean memory → Korea Instrument/TSE, US/EU foundries → FormFactor/Technoprobe); technology segmentation (cantilever, vertical, MEMS each serve different niches with enormous legacy installed bases); and just-in-time delivery speed favoring local/regional suppliers. ATE cross-investments matter for interoperability: Advantest holds a minority stake in FormFactor; Teradyne invested $516M in Technoprobe; JEM has no ATE partner.

X-ray metrology: seeing into 3D structures that light cannot penetrate

All X-ray analytical techniques exploit the interaction between X-ray photons and matter; they differ in what interaction they measure and what information it yields.

X-Ray Diffraction (XRD). Monochromatic X-rays hitting a crystalline material scatter off atomic planes and constructively interfere at specific angles per Bragg's Law: nλ = 2d sinθ, where d is atomic-plane spacing and θ the incidence angle. Scanning the detector across angles reveals crystal structure, phase identity, lattice strain, crystallographic orientation, epitaxial film thickness, and solid-solution composition (e.g., SiGe alloys). High-Resolution XRD (HRXRD) is the workhorse for epitaxial thin films and multilayer stacks.

X-Ray Fluorescence (XRF). An incident beam ejects inner-shell electrons; as outer-shell electrons fill the vacancy they emit secondary X-rays at energies characteristic of each element. Measuring the energy spectrum identifies elements and concentrations. Energy-Dispersive XRF (EDXRF) uses a silicon semiconductor detector to sort photons by energy — faster, lower resolution. Wavelength-Dispersive XRF (WDXRF) uses analyzing crystals via Bragg diffraction — higher precision and sensitivity, slower. In fabs, XRF measures thin-film thickness (metal barrier/seed layers), composition, and contamination. Total Reflection XRF (TXRF) uses grazing incidence for extreme surface sensitivity, detecting trace metal contamination on cleaned wafers down to ~10^8 atoms/cm².

Small-Angle X-Ray Scattering (SAXS). Measures scattering at very small angles (0.1-5°), encoding nanoscale features — pore sizes, particle sizes, periodic nanostructures in the 1-100 nm range. Critical Dimension SAXS (CD-SAXS), developed at NIST and now commercializing, non-destructively measures 3D profiles of periodic nanostructures (FinFETs, GAA nanosheets, 3D NAND channel holes) including sidewall angle, line width, pattern depth, and overlay from a single scattering measurement. Transmission geometry characterizes structures deeper than 1 µm (3D NAND, DRAM); reflection geometry handles a few nm to ~200 nm (GAA, CFET).

X-Ray Reflectometry (XRR). Measures X-ray intensity reflected at grazing angles; interference fringes in the reflectivity curve (from reflections at different layer interfaces) yield film thickness (sub-nm to hundreds of nm), density, and interface roughness for crystalline and amorphous materials. Critical for monitoring gate dielectrics, barrier layers, and multilayer stacks.

Technique-to-application map:

Technique	What It Measures	Semiconductor Application
HRXRD	Crystal structure, strain, composition, epi thickness	Epitaxial QC (SiGe, III-V, GaN-on-Si), substrate orientation
XRF/TXRF	Elemental composition, film thickness, contamination	Metal layer thickness, barrier integrity, wafer cleanliness
SAXS/CD-SAXS	3D nanostructure dimensions	CD metrology for FinFET, GAA, 3D NAND
XRR	Film thickness, density, roughness	Gate oxide, low-k dielectric, multilayer stacks

X-ray vs. optical — the complementarity, not competition. The broader semiconductor metrology market (~$13-15B) is dominated by optical techniques — optical scatterometry (OCD), spectroscopic ellipsometry, optical inspection — led by KLA (55-63% of wafer inspection share). Optical is very high throughput (seconds per measurement), measures surface/near-surface topography, CD, overlay, but struggles with high-aspect-ratio 3D structures and is model-dependent. X-ray is historically slower (source-brightness constrained) but offers non-destructive depth profiling, material-specific information, and model-independent 3D structural data. The key insight: as devices go three-dimensional (GAA transistors, 200+ layer 3D NAND, HBM stacks), light cannot penetrate deep high-aspect-ratio features, so X-ray becomes an essential complementary tool, not a replacement. X-ray metrology vendors like Rigaku are not competing head-to-head with KLA or ASML; the overlap is with other thin-film approaches (optical ellipsometry, e-beam) for specific steps.

Where X-ray tools deploy across the fab. FEOL: HRXRD for epitaxial layers (SiGe channels, III-V), XRR for gate-oxide thickness/density, TXRF for wafer cleanliness. BEOL: XRF for metal (Cu, W, Co, Ru) barrier/seed thickness, XRR for low-k dielectric. Packaging: XRF for bump composition (SnAg solder), CD-SAXS for TSV characterization, X-ray topography for defects. In advanced packaging specifically, detecting sub-micron voids and cracks in 20 µm micro-bumps, controlling SnAg solder composition, and measuring Cu pillar height all require X-ray.

Inline vs. offline. Inline (in-fab) tools sit on the production floor, connected to MES, measuring production wafers in real time — premium pricing, deep customer lock-in through fab-automation integration. Offline (lab-based) tools serve R&D, failure analysis, reference metrology. Inline semiconductor X-ray metrology is effectively a Rigaku-Bruker duopoly, with Malvern Panalytical (Spectris) entering after acquiring Freiberg Instruments' XRD products in 2024.

The oligopoly's physics-and-process moat. X-ray instrument design spans X-ray physics, optics (mirrors, monochromators, collimators), detector technology, precision mechanics (goniometers with arc-second precision), and application-specific algorithms. Rigaku alone has 70+ years of expertise and 35+ years inline. The CD-SAXS field hinges on patents around compact high-brilliance X-ray sources critical for inline throughput. Fab qualification runs 12-24+ months (tool-of-record qualification, correlation studies against existing methods, SECS/GEM integration, long-term uptime demonstration). Switching costs are exceptional: 12-24 months re-qualification, hundreds of measurement recipes to re-develop, historical data continuity broken, automation interfaces rebuilt, yield error worth millions, engineers retrained. Service/parts/consumables (X-ray tubes)/software run 20-30% of original instrument price per year, creating a self-reinforcing installed-base advantage. Risk to the moat: if compact high-brilliance X-ray sources don't improve fast enough, CD-SAXS may not reach the inline throughput high-volume manufacturing demands.

Engineered substrates and deposition equipment: the materials and tools that enable everything upstream

Smart Cut engineered wafers. Soitec buys commodity silicon, applies its patented Smart Cut process — effectively an atomic scalpel that cleaves off a crystal-thin layer and bonds it to an insulating substrate — and sells the resulting engineered SOI substrate to foundries at a large markup. It is a pure materials company (100% product revenue). The product is consumed (wafers are used up), so demand is inherently smoother than for capital goods; chip designs lock in the substrate for the product's lifetime, making transactional sales highly recurring in practice. The moat is among the deepest in semis: 4,300+ patents plus a Smart Cut monopoly, with 70%+ share of a SOI wafer market of ~$1.5B today growing to $2.5-3.3B by 2029-2033. Photonics-SOI is the highest-conviction growth vector — every 800G/1.6T optical transceiver needs SOI wafers (growing ~27% YoY); RF-SOI is 61% of revenue tied to the smartphone cycle; POI (piezoelectric-on-insulator) adoption is validated by a Skyworks multi-year supply agreement.

MOCVD deposition systems. Aixtron makes the machines that grow compound-semiconductor layers (GaN, SiC, InP) atom-by-atom onto wafers via Metal-Organic Chemical Vapor Deposition. This is capital equipment — ~80% one-time equipment sales, ~20% recurring aftermarket service; orders are lumpy, tied to customer capex cycles, and a machine lasts years. The moat is IP/patents plus switching costs plus installed base: 306 patent families, 77% MOCVD share, 27% SiC CVD share, of a MOCVD + SiC CVD equipment market of ~$1.05B. End markets: GaN/SiC power electronics, optoelectronics (AI laser demand via the G10-AsP platform), LED/micro-LED. The 300mm GaN transition is a multi-year platform upgrade driving a new equipment cycle. The consumed-product-vs.-capital-good distinction is decisive: a materials maker (Soitec) has more predictable recurring demand than an equipment maker (Aixtron), whose sales arrive in cycles only partially smoothed by a service tail.

IC substrates (ABF FC-BGA). The physical connection layer between chips and the circuit board. AT&S is the #5 ABF IC substrate maker (~8% share) and the only scaled European player, making ABF FC-BGA substrates for AI accelerators and HDI PCBs for mobile/auto/industrial. The economic driver is a structural supply shortfall: the ABF substrate market is ~$10B+ (2027E) with undersupply widening to ~10% in H2 2026 and 42% by 2028, driving ASP expansion ($65 → $82 already). Incremental EBITDA margins on new capacity run ~40%. This is contract manufacturing — high customer concentration, OEM qualification barriers (12-24 months), and geography as moat.

Glass-core substrates and TGV drilling. The next-generation package substrate, developed (notably by Intel for its EMIB-T platform) as an alternative to organic ABF. The enabling process step is Through-Glass Via (TGV) drilling via laser micromachining — E&R Engineering's core relevant technology. TGV is a near-zero market today (pre-commercialization); the economics are entirely optionality on the glass-substrate ramp (2027-28).

Semicap subsystems. The precision modules inside the capital equipment that builds chips — gas delivery modules, chemical delivery systems, weldments, frame assemblies (Ultra Clean Holdings, supplying AMAT/LRCX/KLA). Roughly 30-40% of an OEM tool's cost of goods traces back to such subsystem suppliers. The economics are a fixed-cost-leverage / operating-leverage play: running at ~65% of a $3B revenue-capable infrastructure, every dollar of WFE recovery flows through at ~35-40 cents of incremental gross profit (on near-zero incremental capex), though base gross margins are structurally thin (~15.7%). The moat is OEM qualification lock-in (12-24 months per platform) offset by extreme customer concentration.

Yield analytics software. The analytics/process-control layer between equipment and fab operations (PDF Solutions' Exensio) — harmonizes data from 50+ formats (FDC, test, assembly, packaging), runs AI/ML models, and monetizes via a Gainshare model where revenue is tied to customers' yield improvements. 94% recurring revenue, ~76% gross margin, 80%+ incremental gross margin on new SaaS revenue. The moat is multi-layer data infrastructure and operational integration — once Exensio is in a fab, switching means remapping 50+ data formats, retraining teams, and losing years of process intelligence.

Advanced-packaging inspection. The quality gate every EMIB, CoWoS, and HBM packaging line requires — Onto Innovation's Dragonfly systems inspect bump heights, die-to-die alignment, and defects; Atlas handles OCD metrology for leading-edge logic. Capital equipment with high post-install switching costs and a growing service tail; the AI-packaging cycle and 2nm GAA transition raise inspection intensity per wafer step.

The cross-cutting economic drivers

Several first-principles forces increase test/metrology intensity — spend per wafer step — independent of unit volume, and they recur across every theme above:

Node shrinkage and the FinFET → GAA transition (at 3nm/2nm) introduces new metrology challenges (channel thickness, composition, strain across stacked nanosheets) and raises TDDB burn-in intensity. Every architecture transition increases metrology spend per wafer step. (TSMC's 2nm CMOS logic platform is the reference node for this transition.)
3D NAND scaling to 200-300+ layers makes high-aspect-ratio channel-hole, charge-trap, and word-line measurement nearly impossible for optical methods, pulling in X-ray (CD-SAXS, XRR).
Advanced packaging and HBM (CoWoS, InFO, EMIB, Foveros, SoIC) require KGD testing of every chiplet before assembly; a single advanced package can contain 5-10+ dies from different nodes, each needing its own probe-card design and its own metrology recipe, multiplying unique designs per product.
New materials proliferation — high-k dielectrics, ruthenium/cobalt interconnects, SiGe channels, III-V compounds — each requires the crystal-quality, composition, and contamination characterization that XRD/XRF excel at.
Rising packaging cost dramatically raises the economic penalty for packaging a bad die, pushing more test insertions earlier (the "test everything at wafer level" trend) — more insertions = more probe-card and burn-in demand.

The follow-the-capex chain. Hyperscaler AI infrastructure spend (NVIDIA $100B+, Microsoft $80B, Meta $40B) → SK Hynix/Samsung/Micron HBM ramp at 30-50% CAGR → equipment orders (FOX-XP, probe cards, metrology) on a 6-12 month lag → consumable replacement cycles (WaferPaks, probe cards) arriving continuously, the compounding second-derivative leg 12-18 months after system installation.

Revenue pools and TAM builds.

Burn-in revenue pools:

Segment	2024E TAM	2028E TAM	CAGR
Wafer-level burn-in (systems + WaferPaks)	~$500-700M	~$1.5-2.5B	30-40%
Package-level burn-in (ovens + BIBs)	~$400-600M	~$500-700M	5-8%
Burn-in sockets/consumables	~$250-400M	~$350-550M	8-12%
Total	~$1.2-1.7B	~$2.4-3.7B	~20-25%

Probe card TAM: ~$2.1-2.6B in 2024, growing to ~$3.3-4.2B by 2030-2032 at a 6-10% CAGR (range reflects scope: some include substrates/accessories). HBM is the dominant driver — the HBM market is projected at $54.6B in 2026 (+58% YoY), with Samsung and SK Hynix shipping >250M HBM stacks in 2025. Probe-card market by application: Foundry/Logic ~35%, DRAM incl. HBM ~30-35%, NAND ~10-15%, Other ~15-20%.

X-ray analytical instruments TAM: ~$2.2-2.5B (2024-25) — XRD instruments ~$760M-$1.0B, XRF analyzers ~$1.5B — growing 3-5% CAGR. The semiconductor X-ray metrology sub-segment is sub-billion ($300-500M range) but growing 15-25% CAGR, far outpacing the broader analytical market. The broader semiconductor metrology and inspection equipment market is ~$9.0-15.0B, growing 5-7% CAGR. XRD share is concentrated: Rigaku ~26-29%, Bruker ~22%, Thermo Fisher ~15%, Malvern Panalytical ~10-12%, Shimadzu ~5-8%; top 3 hold >60%.

How money flows through the chain (per the supply-chain map): foundries/IDMs (TSMC, Samsung, Intel, SK Hynix, Micron) buy metrology tools (~$13-15B market), ATE testers (~$6-7B, capital, 5-10 yr life), probe cards (~$2.1-2.6B, consumable, replaced every few months to a year), probers (~$1-2B capital), burn-in systems (~$200-400M capital for HBM KGD assurance), and handlers/sockets (~$1-2B final test). The structurally attractive lines are the consumables — probe cards, sockets, WaferPaks, BIBs — because they compound with wafer volume and design diversity rather than arriving in lumpy capex cycles.

For company-specific deep dives see AEHR, AWX, S71, 6855 (JEM), 268A (Rigaku), ONTO, UCTT, PDFS, ATS.VI, 8027, SOI, AIXA, 6777 (Santec), and the standalone primers burn-in-test-primer, xray-semi-metrology-primer, semi-probe-card-primer, and semi-test-supply-chain.

Subsectors

The semiconductor capital equipment and test sector is not one market. It is a stack of distinct sub-areas, each with its own technology, its own competitive structure (some monopoly, some duopoly, some fragmented), and its own investment angle. The single most useful distinction running through all of them is capital equipment vs. consumable: capital equipment (litho, etch, deposition, ATE testers, probers, burn-in ovens, metrology tools) is bought once per fab line, lasts 5-10 years, and produces lumpy revenue tied to fab construction; consumables (probe cards, test sockets, WaferPaks, burn-in boards, X-ray tubes) are consumed in production and replaced on design-cycle and wear-out cadences, producing more recurring, compounding revenue. The second cross-cutting distinction is front-end (during fabrication) vs. test/inspection (verifies what was built). What follows enumerates each subsector.

WFE major tools — deposition, etch, litho

Wafer Fab Equipment (WFE) is the front-end manufacturing stack: epitaxy, lithography, deposition, etch, CMP, ion implant, anneal. This is the largest pool of semicap spend and the most concentrated. The canonical peer list is Tokyo Electron, ASML, AMAT (Applied Materials), KLAC (KLA), LRCX (Lam Research). Lithography is effectively an ASML monopoly (EUV). Etch and deposition are dominated by Applied Materials, Lam, and Tokyo Electron. KLA sits at the process-control end (covered under metrology/inspection below).

The structural driver flagged across the sources is transistor scaling and architecture transition. IMEC (Belgium-based research house, a few hours' drive from ASML) called out backside power delivery (BSPDN) as a clear performance advantage; implementing BSPDN in manufacturing requires more etch and deposition tools. Every architecture transition — FinFET to GAA (gate-all-around) nanosheet at 3nm/2nm, then CFET — raises the number of process steps and therefore WFE intensity per wafer. TSMC's 2nm CMOS platform (the GAA node) is the live example of this transition cycle. Note "semicap intensity" (capex as a share of revenue) and "semicap yield by player" are the framing metrics to track here; these were flagged as open research items, not resolved with figures, in the source material.

The WFE subsector connects directly into the test/inspection subsectors below: the WFE buildout (TSMC Arizona, Samsung Taylor, Intel Ohio/Oregon/Ireland, Rapidus/Japan's JPY 2T fab allocation, European Chips Act fabs) is the leading indicator for every downstream test and consumable market. Investment angle: the WFE majors are the most direct, most liquid expression of the capex cycle, but also the most priced. The under-covered angle is the subsystems layer (below) that captures WFE recovery at high incremental margin, and the consumables that compound with wafer volume regardless of which OEM wins the tool order.

Metrology & inspection — X-ray, optical, e-beam

Metrology and inspection (process control) verifies films, dimensions, defects, and contamination — both inline (on the production floor, tied into the fab's MES/Manufacturing Execution System) and offline (R&D/quality labs). The total semiconductor metrology and inspection equipment market is estimated at $9.0-15.0B (2024-2025, estimates vary), growing 5-7% CAGR. It splits into three physics families:

Optical is the dominant family and the broadest market. Optical scatterometry (OCD), spectroscopic ellipsometry, overlay, and optical defect inspection. KLA (KLAC) is the leader at ~55-63% of wafer inspection / process-control share. Onto Innovation (ONTO) is the niche #2-3 — optical film metrology and overlay, plus advanced-packaging inspection via its Dragonfly systems (bump heights, die-to-die alignment, defect detection on EMIB/CoWoS/HBM lines) and Atlas OCD for leading-edge logic. Nova (NVMI) runs a growing hybrid optical + X-ray approach. Lasertec (6920) holds a monopoly in EUV mask/pellicle inspection — a distinct niche with no X-ray overlap. See ONTO, KLAC, NVMI, 6920.

X-ray is a smaller (~$300-500M for the semiconductor sub-segment) but strategically growing niche, expanding 15-25% CAGR — far faster than the broader analytical-instruments market (the all-end-market X-ray analytical TAM is ~$2.2-2.5B, growing only 3-5%). The semiconductor-specific inline X-ray metrology market is effectively a Rigaku-Bruker duopoly, with Malvern Panalytical (Spectris) entering. The four core X-ray techniques:

XRD / HRXRD (X-ray diffraction; Bragg's Law, nλ = 2d sinθ): crystal structure, strain, composition, epitaxial layer thickness. Workhorse for SiGe channels, III-V, GaN-on-Si.
XRF / TXRF (X-ray fluorescence): elemental composition, film thickness (metal barrier/seed layers), contamination. TXRF (grazing-incidence) detects trace metal contamination down to ~10^8 atoms/cm².
XRR (X-ray reflectometry): film thickness (sub-nm to hundreds of nm), density, interface roughness — for gate dielectrics, low-k, multilayer stacks.
CD-SAXS (Critical Dimension Small-Angle X-ray Scattering): emerging, NIST-developed, now commercializing. Non-destructive 3D profiles of periodic nanostructures (FinFET, GAA nanosheets, 3D NAND channel holes) — sidewall angle, line width, depth, overlay from a single scattering measurement.

The X-ray investment thesis is the optical-vs-X-ray divergence at advanced nodes. Optical is faster (seconds per measurement) and mature inline, but light cannot penetrate deep high-aspect-ratio 3D features. As devices go 3D (GAA, 200-300+ layer 3D NAND, HBM stacks), X-ray becomes essential as a complementary tool, not a replacement. Rigaku (268A) is the dominant inline semiconductor X-ray vendor (XTRAIA product family: MF-3400, XT Series, CD-3200T, TF Series, ONYX 3200) with 35+ years of fab-tool leadership; ONYX 3200 targets advanced packaging / HBM micro-bump inspection. Bruker (BRKR) competes via its JV Fab line. See 268A, BRKR.

E-beam is the third family. Applied Materials' PROVision and eScan e-beam metrology, and ASML/HMI (Hermes Microvision) e-beam review. Different physics, competing for some of the same process-control budget.

Investment angle across metrology: formidable moats — 12-24+ month tool-of-record qualification cycles, recipe libraries, installed-base service revenue (typically 20-30% of instrument price per year, X-ray tubes as consumables), and switching costs that make these "sticky" once a vendor is established. The angle differs by family: KLA is the dominant, priced incumbent; Onto is the advanced-packaging-inspection pure-ish play with KLA-encroachment risk; Rigaku/Bruker are the X-ray duopoly riding the 3D-device penetration curve; Nova is the hybrid optimist. Key risk for X-ray specifically: if compact high-brilliance X-ray sources don't improve fast enough, CD-SAXS may never reach the inline throughput high-volume manufacturing needs.

Burn-in & system-level test (SLT)

Burn-in is reliability screening — subjecting devices to elevated temperature (105-130°C, sometimes 175°C+) and/or voltage (1.1-1.3× nominal) for a controlled period to precipitate "infant mortality" failures before delivery. The physics is Arrhenius acceleration (k = A × e^(-Ea / kT)); a device at 125°C ages roughly 10-100× faster than at 25°C, compressing weeks of field aging into hours. It screens TDDB (time-dependent dielectric breakdown — the dominant concern at 3nm/2nm where gate dielectric is atoms-thick), electromigration, hot carrier injection, stress migration, and soft breakdown. This is a distinct subsector that for most of semiconductor history was an unglamorous cost center and is now structurally inflecting on three forces: the AI-accelerator quality story, the HBM ramp (Known Good Die requirements on every stacking line), and Intel 18A re-entry (chiplet/advanced-packaging qualification burden).

The subsector splits sharply into wafer-level vs package-level:

Attribute	Package-Level	Wafer-Level (WLBI)
When	After packaging	Before dicing
KGD capable	No	Yes
Parallelism	Moderate (16-64/board)	Full wafer (highest possible)
Capital cost	$200K-$1M per oven	$3-5M per system
Throughput	~3,200 devices/cycle	10,800+ dies/cycle (18 wafers × 600)
Cost per device	$0.05-$0.50	$0.02-$0.15
Key vendor	TESEC (Advantest), Sunright, Chroma	Aehr Test (dominant)
Trend	Declining for advanced	Rapidly growing (HBM)

Wafer-level burn-in (WLBI) is the high-growth leg, dominated near-monopoly by Aehr Test Systems (AEHR) with its FOX-XP system (up to 18 wafers parallel, $3-5M ASP) and the proprietary WaferPak full-wafer contact consumable ($80K-$180K, 30K-50K contacts). The stack-yield math forces it: at 97% per-die yield, an 8-die HBM stack yields ~78%; getting to 99.5% via burn-in raises stack yield to ~96% — worth thousands of dollars per package. WLBI is in the critical path of every HBM line at SK Hynix, Samsung, Micron. SiC power devices are a separate captive WLBI market (basal-plane-dislocation bipolar degradation mandates 100% screening for automotive ASIL-D / 0 DPM). Aehr's emerging DiePak addresses bare-die / chiplet KGD before assembly. See AEHR.

Static vs. dynamic burn-in: static holds fixed inputs at stress (screens TDDB/EM, cheap, misses logic-path defects); dynamic runs functional vectors during stress (broader coverage, standard for complex logic). System-Level Test (SLT) is effectively dynamic burn-in plus system context — running the chip in conditions mimicking real-world use to catch defects wafer-probe and final-test miss. SLT is "Growing in Importance" because AI chips are too complex for traditional test alone; it supplements, does not replace, wafer probe. Advantest and Teradyne lead SLT; Teradyne's Mercury platform is adjacent to dynamic burn-in. AEM Holdings (AWX.SI) is a burn-in handler + SLT-cell maker whose PiXL Active Thermal Control handles >2,000W per package (modern AI accelerators), anchored on Intel (~55-65% of revenue). See AWX.

WLBI burn-in TAM build (systems + consumables + sockets):

Segment	2024E TAM	2028E TAM	CAGR
Wafer-level burn-in (systems + WaferPaks)	~$500-700M	~$1.5-2.5B	30-40%
Package-level burn-in (ovens + BIBs)	~$400-600M	~$500-700M	5-8%
Burn-in sockets/consumables	~$250-400M	~$350-550M	8-12%
Total	~$1.2-1.7B	~$2.4-3.7B	~20-25%

Package-level burn-in is the slower, low-barrier, price-competitive leg — multiple Asian manufacturers compete. Ovens: TESEC (Advantest subsidiary, $500K-$1.5M/oven), Sunright (S71.SI) (burn-in-as-a-service + KES Systems, the world's leading burn-in board / BIB maker; also holds 48.4% of KESM Industries, Malaysia's largest independent burn-in/test provider for automotive ICs), Chroma ATE (2360) (SiC/GaN power burn-in). See S71, 2360.

Investment angle: the WaferPak consumable stream is the under-priced compounding leg — at ~$120K per WaferPak and 30K contact life, high-volume DRAM fab throughput implies $2M+/month per major customer, arriving 12-18 months after system installation (a second-derivative pattern). The serious bear risk is Advantest developing a credible WLBI product and qualifying at Samsung. The two Singapore-listed burn-in plays (AWX and S71) are different risk profiles on the same theme: AWX is the higher-quality, higher-ceiling equipment/SLT play (priced for its bull case); S71 is the near-zero-EV SOTP value play (net cash + KESM stake ≈ market cap, operating business priced at roughly negative S$53M).

Probe cards & test consumables

Probe cards are the electromechanical interface used at wafer probe / wafer sort (CP test) — the first electrical test on devices while still on the wafer, before dicing and packaging. The card is a specialized PCB fitted with microscopic contact probes, sitting between the wafer (on a prober chuck) and the ATE tester. It identifies Known Good Die (KGD), preventing the packaging of defective dies — critical because for multi-die packages (chiplets, HBM stacks, SiP) a single bad die can scrap an assembly costing hundreds to thousands of dollars; KGD improves final package yield by >10%.

The defining investment attribute: probe cards are consumables, not capital equipment. Each new device design, design revision, or shrink requires a new card; cards wear out after millions of touchdowns. A single fab may run hundreds of distinct probe-card designs simultaneously. Revenue compounds with both wafer volume AND design complexity/diversity — a structural tailwind as the industry fragments into more chiplet and HBM variants. Three technologies:

Feature	Cantilever	Vertical	MEMS
Probe orientation	Horizontal needles	Perpendicular	Microfabricated springs
Pad pitch	Coarse (>100 µm)	Fine (60-100 µm)	Ultra-fine (<50 µm)
Pin count	Low-moderate	Moderate-high	Very high (200K+)
Touchdown life	500K-2M	up to 5M	10M+
Primary use	Analog, legacy logic, driver ICs	Advanced logic, RF, GPUs	Leading-edge logic, DRAM, HBM, adv. packaging
Key players	JEM (strong)	FormFactor, MPI	FormFactor, Technoprobe, MJC

Probe-card TAM was ~$2.1-2.6B in 2024, growing to ~$3.3-4.2B by 2030-2032 at 6-10% CAGR. Unlike litho (ASML monopoly) or ATE (Advantest/Teradyne duopoly), this market is fragmented (5+ meaningful players, top-5 ~73% share) because every design needs a unique card, qualification is customer-specific, regional preferences are strong (Japanese fabs favor JEM/MJC, Korean memory makers favor Korea Instrument/TSE), technology is segmented, and delivery speed favors regional suppliers. Players:

FormFactor (FORM) — #1, ~30% share; broadest portfolio (logic, DRAM, NAND, HBM); R&D >15% of revenue; $764M FY2024 revenue; HBM revenue quadrupled in 2024; ships to all three HBM makers; Advantest holds a minority stake.
Technoprobe (Italy, private) — #2, ~15-18%; MEMS leader; won ~30% of TSMC 2nm qualifications; Teradyne invested $516M.
Micronics Japan / MJC (6871) — #3, ~14%; #1 in memory probe cards.
Japan Electronic Materials / JEM (6855) — #4-5, ~5-7%; cantilever heritage, ~$176M TTM revenue, transitioning toward advanced cards; benefits from Japan domestic-sourcing mandates; Kumamoto plant expansion near TSMC's new fab; the central question is whether it can move beyond cantilever to MEMS or be confined to the slower legacy segment.
MPI (6223.TW) — #4-5, ~5-7%; ultrasonic self-cleaning tips (extend life 50%); integrated prober + card.
Korean: Korea Instrument, TSE (probe-card revenue +90% YoY 2025). Chinese (~2% share): MaxOne, Shanghai Zenfocus, JUNR/Wuxi Junr.

HBM probe cards are the hardest and highest-value: up to 150,000 pins (3× standard DRAM), contacting ~4,000 micro-bumps per die at 45-55 µm pitch / 25 µm bump diameter, full-wafer single-touchdown, >4 GHz signal integrity, severe thermal management, and CTE-mismatch alignment drift. Pricing: leading-edge card >$2.5M; standard DRAM card $200-300K; HBM card $500K-1M+. Contact current density now exceeds 15 mA/µm² at advanced nodes, halving tip lifetimes and raising replacement frequency.

Adjacent test consumables at final test: test sockets — Yamaichi Electronics (6941) is Japan's leading socket maker (burn-in + final test, ~40-50% gross margins; every new HBM package generation and pin-count increase needs new socket designs), plus 3M/Textool, Sensata, Ironwood. Burn-in boards (BIBs) — KES Systems (Sunright). Investment angle: the consumable dynamic is the prize — design-locked, wear-driven, compounding with volume × design diversity. The headwind is that MEMS' longer life (10M+ touchdowns) means fewer replacement units per fab even as ASPs rise; and probe-card demand is cyclical (the market fell ~18% in 2023 in the memory downturn). See FORM, 6855, 6871, 6941.

ATE — automated test equipment

ATE (the tester) is the capital-equipment core of test, used at both wafer probe (Stage 2) and final test (Stage 4), and into SLT (Stage 5). It executes test programs, applies vectors, and records pass/fail. The total ATE market is ~$6-7B. Structure is a clean duopoly:

Advantest (6857) — #1, ~55-60% ATE share; dominant in memory test; owns TESEC (package-level burn-in) integrating burn-in into the ATE workflow; benefits from every HBM ramp (more test + more burn-in volume). The notable gap: Advantest does not yet make wafer-level burn-in equipment — the revenue gap Aehr fills, and the most-watched competitive question in the burn-in subsector.
Teradyne (TER) — #2, ~30-35% share; dominant in SoC (Apple, Qualcomm); higher gross margins (~55%) than Advantest; more SoC- than memory-cycle exposed; Mercury SLT platform; invested $516M in Technoprobe.
Cohu (COHU) — #3, smaller; test handlers + contactors + some ATE.

Test-equipment spending surged 48.1% in 2025 driven by complex AI architectures. The cross-investment pattern matters: Advantest→FormFactor (minority), Teradyne→Technoprobe ($516M) — these tie ATE makers to probe-card IP and guarantee interoperability (probe cards must be electrically compatible with specific ATE platforms). Investment angle: the ATE duopoly is the lower-volatility, multi-year holding within test — it captures every test-intensity step-up (AI complexity, HBM, SLT growth) without the single-product binary risk of the smaller players. Competitive note from the comparison set: Keysight's R&D budget ($1B+) exceeds Anritsu's entire revenue, and a Teradyne/MLTP JV is a direct threat in optical/comms test-and-measurement adjacency.

Subsystems

Subsystems are the precision components inside WFE tools — gas-delivery modules, chemical-delivery systems, weldments, frame assemblies — sold to the WFE OEMs (AMAT, LRCX, KLA). Roughly 30-40% of a WFE tool's cost of goods traces to subsystem-style suppliers. The bellwether is Ultra Clean Holdings (UCTT): ~$2B revenue, customers AMAT + LRCX = 57% of revenue (extreme concentration), structurally thin gross margins (~15.7%). The model is high-operating-leverage: UCT runs at ~65% of its $3B revenue-capable infrastructure, so every dollar of WFE recovery flows through at ~35-40 cents of incremental gross profit. Investment angle: a rate-of-change play on WFE recovery (15-20% guided FY2026) and the Intel 18A ramp (AMAT/LRCX Ohio/Arizona/Ireland tool deliveries) — utilization recovery from 65% toward 80%+ delivers margin expansion at near-zero incremental capex. Caveats: the most commoditized model in the chain, customer-insourcing tail risk, and (UCTT-specific) a pending securities-fraud class action. See UCTT.

A related software/analytics "subsystem" layer sits between equipment and fab operations: PDF Solutions (PDFS) — Exensio yield analytics, 94% recurring revenue, ~76% gross margin, a Gainshare model tying revenue to customers' yield improvements, Cimetrix equipment-communication software embedded in every major OEM's SDK, and a public Intel co-development endorsement. Highest business quality and most durable model in the advanced-packaging comparison set. See PDFS.

Advanced-packaging tools — laser, plasma, TGV

As value migrates from the transistor to the package (CoWoS, InFO, EMIB, Foveros, SoIC, hybrid bonding), a distinct tool subsector serves assembly. This is where Intel's 18A / EMIB-T platform and the glass-core substrate transition concentrate. Tools and players:

Laser micromachining / plasma processing — E&R Engineering (8027.TWO): laser TGV (Through-Glass Via) drilling for glass-core substrates (Intel's next-gen alternative to organic ABF for EMIB-T) plus plasma processing; TGV customer is a Japanese substrate maker, North American revenue from AIS integration for an NA IDM. Pre-commercialization / option-priced; competes with DISCO, Coherent, 3D-Micromac in laser processing. See 8027.
Dicing / grinding / laser saws — DISCO (6146), dominant in dicing.
Advanced-packaging inspection — Onto Innovation's Dragonfly (covered under metrology) is the quality gate every EMIB/CoWoS/HBM line requires.
Hybrid bonding — BESI volumes are a proxy for 3D-IC assembly intensity (which drives KGD/burn-in demand). 3D-IC stack burn-in (burn-in on partially assembled stacks) is at R&D stage (IMEC, national labs), a 3-5 year horizon that would add a new step to the packaging flow.
IC substrates (the package's connection layer, adjacent to tools) — AT&S (ATS.VI): world's #5 ABF FC-BGA substrate maker, the only scaled European player (~8% share), Kulim/Malaysia ramp with AMD; the substrate shortfall is structural (10% in H2 2026, 42% by 2028). See ATS.

Investment angle: advanced packaging is the highest-growth, most-fragmented frontier — multiple non-overlapping layers (substrate → laser/TGV tooling → inspection → bonding → yield analytics). The "showdown" conclusion across ATS.VI / ONTO / UCTT / PDFS / 8027.TWO is that the theme is real but most names have already re-rated hard; the layered combination (substrate + analytics + inspection) diversifies across the supply chain with minimal overlap, while the laser/TGV play (8027) is option-priced on a pre-commercial market and the subsystems play (UCTT) is the most commoditized.

Compound-semi deposition — MOCVD

Compound semiconductors (GaN, SiC, InP, GaAs) require their own deposition equipment and engineered substrates — a subsector distinct from silicon WFE. MOCVD (Metal-Organic Chemical Vapor Deposition) systems grow compound-semi layers atom-by-atom onto wafers. The dominant tool vendor is Aixtron (AIXA): 77% MOCVD share, 27% SiC CVD share, 306 patent families; revenue split Power Electronics (GaN+SiC) 57% / Optoelectronics 23% / LED/Micro-LED 15% / Service 20%; the G10 platform families (G10-AsP for AI lasers, G10-SiC, 300mm GaN via the Innovation Center) drive the equipment cycle. Demand vectors: AI data-center power and optics, EV SiC adoption (currently digesting overcapacity, structural demand resuming ~2027), the 300mm wafer transition, GaN power. See AIXA.

The substrate side of compound-semi is the materials adjacency: Soitec (SOI) makes engineered SOI / POI wafers via its patented Smart Cut process (4,300+ patents, 70%+ SOI share) — RF-SOI for smartphones (61% of FY'25 revenue), Photonics-SOI for AI data-center optical transceivers (Edge & Cloud AI +27% YoY), and POI (Skyworks supply agreement). The Soitec-vs-Aixtron framing is instructive for the subsector: both European monopolists, both cyclical, but Soitec's materials (wafers consumed continuously) is the more durable, smoother model than Aixtron's equipment (lumpy capital good with a 20% recurring service tail). Investment angle: compound-semi deposition is a leveraged play on EV SiC, GaN power, and AI photonics; the equipment vendor (Aixtron) carries lumpier revenue and higher valuation-overshoot risk, the substrate maker (Soitec) carries deeper cyclical troughs but a deeper moat and smoother consumed-product demand. SiC wafer-start guidance (Wolfspeed, Onsemi, STMicro) is the leading indicator for both compound-semi deposition and SiC burn-in demand.

Value chain

The semiconductor capital-equipment and test value chain is a distinct supply chain that runs parallel to the manufacturing chain (litho, deposition, etch, CMP). It does not build the chip; it verifies that what was built actually works, and it does so at five or six checkpoints between bare wafer and shipped part. Money enters at the top from chip designers (NVIDIA, AMD, Apple, Qualcomm), flows to foundries and IDMs (TSMC, Samsung, Intel, SK Hynix, Micron), and then fans out to the equipment and consumable vendors that sit at each test and inspection gate. The structural feature worth internalizing: the largest, most cyclical capital pools sit in lithography and ATE, but the highest-recurrence, hardest-to-displace margin pools sit in the consumables — probe cards, WaferPaks, burn-in boards, test sockets — that get used up against wafer volume rather than purchased once per fab line.

End-to-end map: who does what, in flow order

The full test-and-inspection flow, stage by stage, with the vendors and their market positions:

Stage 1 — In-line metrology and inspection (during fabrication, between process steps). Verifies films, dimensions, defects, and contamination in real time. Three competing physics:

Optical inspection and metrology — KLA (KLAC), ~55-63% of the wafer-inspection / process-control market; the dominant player. Wafer inspection, OCD/scatterometry, overlay. ONTO (Onto Innovation) is the niche #2-3 in optical film metrology and overlay, and the specialist in advanced-packaging inspection (Dragonfly systems — bump heights, die-to-die alignment, defect detection on EMIB/CoWoS/HBM lines). Nova (NVMI) runs a growing optical + X-ray hybrid approach. Lasertec (6920) holds a near-monopoly in EUV mask/pellicle inspection.
X-ray metrology — effectively a duopoly in inline semiconductor X-ray: 268A (Rigaku, ~26-29% of the broad XRD market, the #1 inline semi X-ray vendor with 35+ years and the XTRAIA product family) and Bruker (BRKR, ~22% XRD share, competing with its JV Fab line). Malvern Panalytical (Spectris) is entering. X-ray is complementary to optical, not competitive — as devices go 3D (GAA, 200+ layer 3D NAND, HBM stacks), optical light cannot penetrate deep high-aspect-ratio features, so X-ray (CD-SAXS, XRR, HRXRD, TXRF) gains relevance as a complementary tool.
E-beam inspection/metrology — Applied Materials (AMAT, PROVision, eScan) and ASML/HMI (Hermes Microvision) for e-beam review. Different physics, competes for the same process-control budget on specific applications.

Stage 2 — Wafer probe / wafer sort (CP test; after fab, before dicing). Electrically tests every die on the wafer to identify Known Good Die (KGD). Three subsystems work together, and the capital-vs-consumable split here is the single most important value-chain distinction in the sector:

ATE (Tester)  →  Test Head  →  Probe Card  →  Wafer (on prober chuck)
 (Advantest,      (electrical     (PCB +         (vacuum-mounted,
  Teradyne)        connection)     probes)        aligned by camera)

ATE (tester) — capital equipment. Advantest (6857) ~55-60% share; Teradyne (TER) ~30%; Cohu (COHU) smaller. A near-duopoly; lasts 5-10 years per fab. ~$6-7B market.
Probe card — consumable. FORM (FormFactor) ~30% (#1), Technoprobe ~15-18% (#2), 6871 (MJC / Micronics Japan) ~14% (#1 in memory), 6855 (JEM) ~5-7% (#4-5, #1 in Japan), MPI (6223.TW) ~5-7%, plus Korea Instrument and TSE (Korea). ~$2.1-2.6B market.
Wafer prober — capital equipment. Tokyo Electron (TEL / 8035) dominant, Tokyo Seimitsu (7729), FormFactor also makes probers. ~$1-2B market.

Stage 2.5 — Wafer-level burn-in (for HBM and advanced packaging). Stress testing at elevated temperature/voltage to weed out infant-mortality failures before dies enter a stack. AEHR (Aehr Test) with the FOX-XP system is the dominant, near-monopoly player; Advantest is developing solutions. Probe cards (JEM, FormFactor) are used inside the burn-in process. ~$200-400M market. Burn-in accelerates probe-card wear, creating cross-stage replacement demand.

Stage 3 — Dicing and packaging. DISCO (6146) dominant in dicing (saws, grinders, laser saws); ASE (3711.TW) and Amkor (AMKR) as merchant OSATs; TSMC's CoWoS and Samsung/SK Hynix HBM stacking are done in-house. For HBM, dies are stacked 8-12 high with TSV interconnects; for AI logic, chiplets are assembled on a CoWoS silicon interposer.

Stage 4 — Final test (FT). Tests the packaged chip for speed, power, functionality. Three subsystems again: ATE (Advantest, Teradyne, Cohu); test socket — consumable (6941 Yamaichi, 3M/Textool, Sensata, Ironwood); handler — capital equipment (Advantest, Cohu, Teradyne). ~$1-2B combined for handlers and sockets.

Stage 5 — System-level test (SLT), growing in importance. Runs the chip in a system-like environment to catch defects that wafer probe and final test miss. Advantest and Teradyne (Mercury platform at Teradyne) lead. SLT is additive to wafer probe — AI chips are too complex for traditional test alone — it supplements, it does not replace. AEM Holdings (AWX.SI) makes SLT cells and thermal-management handlers (PiXL Active Thermal Control, >2,000W per package) for this stage; Intel is its anchor at ~55-65% of revenue.

Then shipment to the chip buyer.

Where the margin pools sit, and why

The clearest way to size the pools is to follow the foundry/IDM purchase wallet:

Equipment bucket	Approx. market	Type	Cadence
Metrology/inspection (KLA, Rigaku, Onto)	$13-15B	Capital	Per node transition + fab build
ATE testers (Advantest, Teradyne)	~$6-7B	Capital	Lasts 5-10 years
Probe cards (FormFactor, MJC, JEM)	~$2.1-2.6B	Consumable	Replaced months-to-a-year
Wafer probers (TEL, Tokyo Seimitsu)	~$1-2B	Capital	Per fab line
Burn-in systems (Aehr)	~$200-400M	Capital	Per HBM/SiC line
Handlers + sockets (Cohu, Yamaichi)	~$1-2B	Mixed	Sockets consumable

The capital pools (metrology, ATE, probers) are larger in dollar terms but lumpy and tied to fab-construction and node-transition cycles. The consumable pools (probe cards, burn-in boards, test sockets, Aehr's WaferPak) are smaller in headline TAM but compound directly with wafer volume and design diversity — which is the better business through a cycle because demand recurs continuously instead of arriving in capex waves.

The consumable thesis — the most important value-chain insight

Probe cards are consumables, not capital equipment. Each new device design, design revision, or technology shrink requires a new set; cards wear out after millions of touchdowns. A single fab may use hundreds of different probe-card designs simultaneously. Leading-edge probe cards run >$2.5M each (only the largest fabs can amortize that); standard DRAM cards ~$200-300K; HBM cards command a premium at ~$500K-1M+ on 3x the pin count, tighter pitch, and thermal complexity. This means probe-card revenue compounds with both wafer volume and design complexity/diversity — a structural tailwind as the industry fragments into more chiplet designs and HBM variants.

The same dynamic holds for Aehr's WaferPak (the full-wafer contact interface for wafer-level burn-in: $80K-180K, 30K-50K contacts, customer-specific so non-substitutable without requalification). The under-modeled stream is the replacement WaferPak, not the system: at ~$120K per WaferPak and 30K-contact life, high-volume DRAM-fab throughput implies $2M+/month per major customer. The system order arrives first; the WaferPak replacement stream is the compounding leg that arrives 12-18 months after installation and continues indefinitely. Test sockets (Yamaichi 6941) behave identically — every new HBM package generation and every AI-chip pin-count increase requires a new design-locked socket that then wears with use.

Choke points and bottleneck-tier analysis

Burn-in primer bottleneck ranking (smallest pure-play that gates each layer):

Layer	Smallest pure-play	Market cap	Concentration	Bypassable?	Market priced?
WLBI systems	AEHR	~$350-600M	Near-monopoly	No	Partial
WaferPak consumables	AEHR (captive)	n/a	Monopoly	No	Under-priced
Burn-in sockets (pkg)	Yamaichi 6941	~$400-600M	Moderate	Partial	Roughly priced
Pkg-level BI ovens	Sunright SUN	~$50-80M SGD	Fragmented	Yes	Priced

Top three named choke points: (1) Aehr WaferPak consumables — monopoly, non-bypassable, scales directly with HBM wafer volume; (2) Aehr DiePak — emerging, the only production-ready die-level burn-in for 3D chiplet KGD; (3) HBM probe cards (adjacent) — FormFactor/MJC/JEM at the wafer-sort step, where HBM burn-in acceleration increases card wear.

Beyond burn-in, the genuine choke points across the chain:

Lithography — ASML monopoly (upstream of test, but the binding constraint on the whole chain's leading-edge capacity).
EUV mask inspection — Lasertec near-monopoly.
Inline X-ray metrology — Rigaku/Bruker duopoly; 12-24 month qualification cycles make incumbents extremely sticky.
ATE — Advantest/Teradyne duopoly (>70% combined).
Wafer-level burn-in — Aehr near-monopoly; 12-18 month qualification at SK Hynix/Samsung/Micron, MEMS contact tech built over 25+ years, thermal management to ±1-2°C across 300mm at 175°C, and yield-correlation data requiring hundreds of thousands of devices.
ABF IC substrates — a genuine physical bottleneck: shortfall of 10% in H2 2026 widening to 42% undersupply by 2028; AT&S (ATS.VI) is the only scaled European maker at ~8% share, Unimicron/Ibiden the Asian incumbents. Substrate scarcity is the hard physical gate on AI-accelerator packaging.
TGV (through-glass-via) drilling for next-gen glass-core substrates — pre-commercial, E&R Engineering (8027.TWO) co-developing with a Japanese substrate maker for Intel's EMIB-T platform.

Pricing power, ranked by structure

Pricing power tracks concentration and switching cost, not segment glamour:

Strongest — single-source materials/process monopolies: Soitec (SOI, Smart Cut SOI wafers, 70%+ share, 4,300+ patents, the substrate is locked in for a chip design's lifetime), Aehr's WaferPak (captive, customer-specific), Dexerials (4980, 74% ACF / 93% anti-reflection film). These set price because the customer has no alternative and re-qualification is prohibitive.
Strong — capital-equipment duopolies/oligopolies with long qualification cycles: ASML, Advantest/Teradyne, Rigaku/Bruker, Aixtron (AIXA, 77% MOCVD share for compound-semi epitaxy). 12-24 month tool-of-record qualification, recipe migration across hundreds of recipes, factory-automation integration, and data continuity make switching cost the moat — once installed, retention is multi-year.
Fragmented but defensible — probe cards (5+ players). No single vendor can serve every pad layout, pin configuration, and customer process; regional preference (Japanese fabs → MJC/JEM; Korean memory → Korea Instrument/TSE; US/EU foundry → FormFactor/Technoprobe) and ATE-partnership ties (FormFactor↔Advantest minority stake; Technoprobe↔Teradyne $516M investment; JEM has no ATE partner) segment the market. Customers still push for lower cost-per-touchdown, and MEMS' 10M+ touchdown life means fewer replacement units per fab — a unit-volume headwind even as ASPs rise.
Weakest — package-level burn-in ovens and outsourced burn-in services (Sunright, multiple Asian manufacturers): low barriers, price competition, ~10-20% margins. Avoid as standalone investments; useful only as demand indicators.

Supplier / customer relationships and cross-investments

The chain is knit together by deliberate equity ties that guarantee IP access and interoperability:

Advantest holds a minority stake in FormFactor; Teradyne invested $516M in Technoprobe (and opened a €80M Dresden facility Sep 2025). These lock ATE makers to advanced probe-card IP and ensure probe cards stay electrically compatible with specific tester platforms.
Probe cards must be both electrically compatible with a specific ATE platform and mechanically compatible with a specific prober (TEL, Tokyo Seimitsu). That dual dependency is why probe cards are co-developed with the customer's design team, 4-12 weeks turnaround for standard, longer for leading edge.
Customer concentration runs deep across the chain: TSMC is the single largest probe-card customer in the industry; the top-3 memory makers (Samsung, SK Hynix, Micron) dominate DRAM/HBM demand; Intel anchors AEM (~55-65%) and PDF Solutions' Gainshare model; SK Hynix's $240M volume agreement through 2027 is Onto's most visible demand signal. Loss of any single anchor materially impairs the supplier.
Subsystem suppliers sit one layer further back: Ultra Clean Holdings (UCTT) builds the gas/chemical delivery modules, weldments, and frames inside AMAT/LRCX/KLA tools — roughly 30-40% of a tool's COGS traces to UCT-style suppliers (AMAT + LRCX alone = 57% of UCT revenue). PDF Solutions (PDFS) sits as the analytics/software layer between equipment and fab operations (Exensio harmonizing 50+ data formats, Gainshare tied to customer yield, 94% recurring). These are the deepest-back-in-the-chain plays on the same WFE dollar.

Per-stage and per-unit economics (reproduced from sources)

Burn-in unit economics:

Metric	Package-level	Wafer-level (Aehr FOX-XP)
Throughput	3,200 devices/cycle (100 boards × 32)	10,800+ dies/cycle (18 wafers × 600)
Cycle time	8-168 hr	8-48 hr
Temp uniformity	±3-5°C	±1-2°C (critical for HBM)
Consumable life	25K-50K socket insertions	30K-50K WaferPak contacts
Cost per device	$0.05-0.50	$0.02-0.15 (high-die-count wafers)
Capital cost	$200K-1M per oven	$3-5M per system
KGD capable	No	Yes

The KGD stack-yield math that forces wafer-level burn-in and probe into the HBM critical path: at 97% per-die yield, an 8-die stack yields ~78%; raising each die to 99.5% through burn-in lifts the stack to ~96% — a difference worth thousands of dollars per package. With KGD at $20-40+ per HBM stack and packaging cost rising under 2.5D/3D, the economic penalty for stacking one bad die is what pulls test spend earlier in the flow (more insertions per device = more probe-card and burn-in demand). HBM is progressing 8-high → 12-high → 16-high, multiplying TSV connections to be tested.

Probe-card key specifications (the cost driver behind ASP escalation):

Spec	Standard	Leading edge (HBM)
Pitch	80-200 um	40-55 um
Pin count	5,000-50,000	150,000+ (HBM = 3x standard DRAM)
Contact force	0.5-15 g/probe	lower is better
Planarity	<25 um	<±12.5 um
Touchdown lifetime	500K (cantilever)	10M+ (MEMS)

Contact current density now exceeds 15 mA/um² at advanced nodes, roughly halving probe-tip lifetimes vs 7nm and lifting replacement frequency. HBM cards must contact ~4,000 micro-bumps per die at 45-55 um pitch / 25 um bump diameter with probes thinner than a human hair carrying >1A.

Cyclicality and where it bites the chain

The whole chain is cyclical on 2-3 year semiconductor-capex waves, but the shape differs by position. Capital tools (ATE, probers, metrology) track fab construction and node transitions and feel downturns first — the probe-card market fell ~18% in 2023 then rebounded sharply in 2024-25; semicap revenue broadly troughed in 2023. Consumables dampen but don't eliminate the swing because they ride production volume. Wafer-level burn-in is increasingly tied to the HBM secular trend (3-5+ years, mandatory for every AI accelerator) more than commodity DRAM/NAND pricing, while package-level burn-in lags memory investment by 12-18 months. HBM's structural demand partially decouples the test chain from commodity-memory cyclicality, but not from AI-capex cyclicality. The leading indicators that move the chain: hyperscaler AI capex (NVIDIA $100B+ infra, Microsoft $80B, Meta $40B) → SK Hynix/Samsung/Micron HBM ramp → Aehr/probe-card/ATE orders at 6-12 month lag → consumable replacement stream continuous thereafter.

Cross-references

Company-specific economics live on ticker pages: AEHR, FORM, 6855 (JEM), 6871 (MJC), 6941 (Yamaichi), 268A (Rigaku), ONTO, ATS.VI (AT&S), UCTT, PDFS, 8027 (E&R Engineering). Adjacent primers: burn-in-test-primer, semi-probe-card-primer, xray-semi-metrology-primer, semi-test-supply-chain.

Players

The semiconductor capital equipment and test universe in this vault spans five adjacent layers: in-line metrology/inspection, wafer probe (ATE + probe cards + probers), wafer-level and package-level burn-in, dicing/packaging, and final/system-level test — plus the materials and substrate plays (engineered wafers, MOCVD epi, IC substrates) that feed the front of the line. Most of these markets are oligopolies or near-monopolies; the probe card layer is the conspicuous exception, with five-plus credible players. What follows is positioning per company and the comparative tables that map them against each other. Company-specific deep detail lives on the ticker pages.

Test value chain — company-to-stage map

The single most useful orientation is the test & inspection flow. Each company sits at a defined stage, and the stage determines its cyclicality, revenue model (capital equipment vs. consumable), and HBM exposure.

Company	Ticker	Stage(s)	Role	Market Position
KLA	KLAC	1 (Inline)	Optical wafer inspection & metrology	#1 in process control (~55-63% share)
Rigaku	268A	1 (Inline)	X-ray metrology (XRD, XRF, XRR)	#1 in X-ray analytical (~29% XRD share)
Bruker	BRKR	1 (Inline)	X-ray metrology (competing with Rigaku)	#2 in XRD (~22% share)
Onto Innovation	ONTO	1 (Inline)	Optical film metrology, overlay, advanced-packaging inspection	Niche #2-3 behind KLA
Lasertec	6920	1 (Inline)	EUV mask/pellicle inspection	Monopoly in EUV mask inspection
Nova	NVMI	1 (Inline)	Optical + X-ray metrology	Growing hybrid approach
Applied Materials	AMAT	1 (Inline)	E-beam metrology (PROVision)	Also fab equipment giant
Advantest	6857	2, 4, 5	ATE testers + handlers + SLT + TESEC burn-in	#1 in ATE (~55-60% share)
Teradyne	TER	2, 4, 5	ATE testers + SLT (Mercury)	#2 in ATE (~30% share)
FormFactor	FORM	2	Probe cards + wafer probers	#1 in probe cards (~30% share)
Technoprobe	Private (Italy)	2	MEMS probe cards	#2, Teradyne-backed
MJC	6871	2	Memory probe cards	#1 in memory probe cards
JEM	6855	2	Memory/HBM probe cards	#4-5 globally, #1 Japan
MPI Corp	6223.TW	2	Probe cards + probers	Self-cleaning tip tech
Tokyo Electron	TEL (8035)	2	Wafer probers (also fab equipment giant)	Prober leader in Japan
Tokyo Seimitsu	7729	2, 3	Wafer probers + dicing	Dual role
Aehr Test	AEHR	2.5	Wafer-level burn-in systems (FOX-XP)	Niche leader / near-monopoly in WLBI
DISCO	6146	3	Dicing saws, grinders	Dominant in dicing
Cohu	COHU	4	Test handlers + contactors	#3 in test equipment
Yamaichi	6941	4 (sockets)	Test/burn-in sockets	Leading Japanese socket maker

Cross-investments matter for who gets access to advanced IP: Advantest holds a minority stake in FormFactor; Teradyne invested $516M in Technoprobe. JEM, notably, has NO ATE partner — a structural weakness in the probe-card pecking order.

ATE and test equipment — the duopoly anchors

Advantest (6857) and Teradyne TER together hold >70% of the global ATE market — Advantest ~55-60% (dominant in memory), Teradyne ~30% (dominant in SoC: Apple, Qualcomm). Every HBM ramp drives both. Advantest is the broader play: it spans ATE, handlers, SLT, and — via its TESEC subsidiary — package-level burn-in, integrating burn-in into the ATE workflow. Teradyne carries higher gross margins (~55% vs. Advantest's lower memory-cycle mix), is more SoC-exposed, and its Mercury SLT platform is adjacent to dynamic burn-in. The recurring knock on Advantest from the burn-in lens: not making wafer-level burn-in equipment is a revenue gap that Aehr fills. Both are long-term holdings rather than tactical trades.

Probe cards — the fragmented layer

Probe cards are consumables, not capital equipment: each new device design and each shrink needs new cards, cards wear out after millions of touchdowns, and a single fab runs hundreds of designs simultaneously. Revenue compounds with both wafer volume AND design diversity — a structural tailwind as chiplets and HBM variants proliferate. Leading-edge cards run >$2.5M each; standard DRAM cards $200-300K; HBM cards $500K-1M+ (3x the pin count of standard DRAM, up to 150,000 pins). The market is ~$2.1-2.6B in 2024, growing to $3.3-4.2B by 2030-2032 at 6-10% CAGR. Top 5 hold ~73%.

Company	HQ	Est. Market Share	Strengths
FormFactor (FORM)	USA	~30% (#1)	Broadest portfolio: logic, DRAM, NAND, HBM. R&D >15% of revenue. $764M revenue FY2024 (+15% YoY). HBM revenue quadrupled in 2024; ships to all three HBM makers.
Technoprobe	Italy	~15-18% (#2)	MEMS technology leader. Won 30% of TSMC 2nm qualifications. Fully integrated MEMS tip production. EUR 80M Dresden facility (Sep 2025). Teradyne invested $516M.
Micronics Japan / MJC	Japan	~14% (#3)	#1 in memory probe cards globally. Targeting JPY 65B revenue by FY2026; >20% annual growth target. See 6871.
Japan Electronic Materials / JEM	Japan	~5-7% (#4-5)	Strong in cantilever. ~$176M TTM revenue. Transitioning toward advanced probe cards. Benefits from Japan domestic sourcing mandates. See 6855.
MPI Corporation	Taiwan	~5-7% (#4-5)	Ultrasonic self-cleaning tip tech (extends life 50%). Integrated prober + probe card offering.

Other notable: Korea Instrument (Korea domestic leader, expanding into DRAM/HBM); Nidec SV Probe (MEMS, Nidec subsidiary); TSE (Korea — HBM cards, revenue +90% YoY in 2025); and Chinese entrants JUNR/Wuxi Junr, MaxOne, Shanghai Zenfocus (~2% combined share, competing on speed and price).

JEM 6855 is the canonical vault name here: a pure-play probe-card maker, #4-5 globally and #1 in Japan, with cantilever heritage and a growing HBM book. The investment debate is entirely about technology transition — can JEM move beyond cantilever (now confined to legacy/analog/driver ICs) into MEMS/vertical for advanced nodes, or does it get marginalized as the market shifts to finer pitch and higher pin counts? Technoprobe's MEMS wins at TSMC 2nm are the cautionary signal. At ~$653M market cap on ~$176M TTM revenue (~3.7x sales), JEM trades at a discount to FormFactor that reflects this technology risk. MJC 6871 is the memory-probe-card #1 and the cleaner memory-HBM exposure within the Japanese cohort.

Burn-in — wafer-level monopoly plus the Singapore pair

Burn-in splits into wafer-level (WLBI, the high-growth HBM-driven segment) and package-level (mature, fragmented, low-barrier). The WLBI TAM is ~$500-700M in 2024 going to $1.5-2.5B by 2028 (30-40% CAGR); package-level grows just 5-8%.

Aehr Test AEHR is the only investable WLBI pure-play — near-monopoly on the FOX-XP full-wafer system ($3-5M ASP, up to 18 wafers in parallel) and, more importantly, the captive WaferPak consumable ($80K-180K, 30-50K contacts each). Three reinforcing moats: 25+ years of MEMS contact technology no competitor has replicated at 300mm scale; the WaferPak is customer-specific so there's no substitution without requalification; and 12-18 month qualification cycles at SK Hynix, Samsung, and Micron create compounding switching costs. The under-analyzed leg is the WaferPak replacement stream, which scales directly with HBM wafer volume and arrives 12-18 months after each system install — potentially $200-400M/year TAM by 2027. Bear case: Advantest develops a credible WLBI product and qualifies at Samsung (the most serious risk, no confirmed timeline); SiC/EV demand softness; and the 60-80% cyclical drawdown history. DiePak (bare-die KGD for chiplet pre-assembly) is the emerging optionality.

The two Singapore-listed burn-in plays are covered head-to-head in _compare/awx-vs-s71-showdown:

AEM Holdings AWX designs burn-in handlers, SLT cells, and thermal management. Its PiXL Active Thermal Control platform handles >2,000W per package — required for AI accelerators that commodity handlers can't cool. Intel is the anchor (~55-65% of revenue), with an unnamed AI/HPC customer expected to become #1 by end-FY2026. Moat: ~40 thermal patents, 40,000+ Intel SLT installed base, 15-year relationship. The higher-quality, higher-ceiling business — but at S$6.06 (113x TTM P/E) the stock prices the bull case with no margin of safety; the showdown verdict is WATCH, buy on a pullback to S$4.50-5.00.
Sunright S71 is the fee-for-service side: burn-in/test services, plus subsidiary KES Systems (Dallas), the world's leading burn-in board (BIB) manufacturer, plus a 48.4% stake in KESM Industries (Bursa 9334, Malaysia's largest independent burn-in/test provider for automotive ICs). The thesis is pure SOTP: at S$78M market cap against S$72M net cash + a S$59M KESM stake, the operating business (KES Systems + services) is valued at roughly negative S$53M — "buy because the math is broken." The showdown ranks S71 #1 (BUY, small, SOTP) ahead of AWX, on asymmetry and a hard cash floor, while conceding AWX is the better business.

Package-level burn-in players also appearing in the vault: TESEC (Advantest subsidiary), Sunright/KES, Chroma ATE (2360, SiC/GaN power burn-in, ~$220-280M revenue), and Hangzhou Changchuan (China commodity). Yamaichi Electronics (6941) is the Japanese burn-in/final-test socket maker — design-locked sockets that wear with use; every new HBM package generation and AI-chip pin-count increase forces new socket designs; ~40-50% gross margins.

Burn-in investment rankings (from the burn-in primer)

Rank	Company	Ticker	Thesis	Risk	Horizon
1	Aehr Test	AEHR	Only WLBI pure-play; WaferPak consumable compounding	Med-High	18-36 mo
2	Advantest	6857	ATE duopoly + HBM test franchise + TESEC BI	Medium	Long-term
3	Yamaichi	6941	Burn-in + FT socket consumables; undervalued vs moat	Medium	12-24 mo
4	Teradyne	TER	ATE duopoly + SLT growth	Low-Med	Long-term
5	Chroma ATE	2360	SiC power burn-in; diversified	Medium	12-24 mo

X-ray metrology — the Rigaku-Bruker duopoly

In-line semiconductor X-ray metrology (XRD, XRF, XRR, CD-SAXS) is effectively a duopoly between Rigaku and Bruker, with Malvern Panalytical (Spectris) entering. The broader XRD market (~$2.2-2.5B all-end-markets) is led by Rigaku (~26-29% share), Bruker (~22%), Thermo Fisher (~15%), Malvern Panalytical (~10-12%), Shimadzu (~5-8%); top 3 hold >60%.

Rigaku 268A is the vault's canonical X-ray name: the dominant inline semiconductor X-ray metrology vendor (XTRAIA family — MF-3400, XT Series, CD-3200T, ONYX 3200) with 35+ years of fab-tool experience and ~20% revenue growth in its semiconductor segment in FY2025. X-ray is complementary to — not competitive with — KLA's optical dominance; it gains share precisely as devices go 3D (GAA, 200+ layer NAND, HBM) where light can't penetrate high-aspect-ratio features. Carlyle-backed IPO. Risks: 69% overseas revenue (FX/tariff), export controls to China, and whether compact high-brilliance X-ray sources improve fast enough for CD-SAXS inline throughput.

	JEM (6855)	Rigaku (268A)
Stage	2 (Wafer Probe)	1 (Inline Metrology)
What they make	Probe cards (physical contact)	X-ray instruments (non-contact)
Product type	Consumable (wears out)	Capital equipment (lasts years)
Revenue driver	Wafer test volume + design starts	Fab construction + node transitions
Cyclicality	Very high (memory capex)	Moderate (diversified end markets)
Competitive dynamic	Fragmented (5+ players)	Oligopoly (Rigaku-Bruker duopoly)
HBM exposure	Direct (more pins = more revenue)	Indirect (more layers = more steps)

Advanced packaging supply chain — the Intel 18A / EMIB cohort

_compare/ats-vs-onto-vs-uctt-and-more-showdown runs five plays across different layers of the Intel 18A / EMIB packaging chain. The composite ranking, cheapest-to-most-expensive on growth-adjusted basis and final verdict:

Rank	Ticker	Weighted Score	Verdict	One-line
1	ATS (ATS.VI)	3.80	WATCH → SCALE BUY (staged)	Best PEG; only scaled European ABF substrate maker into a widening shortage; 8x NTM EBITDA
2	ONTO	3.78	SCALE BUY (staged)	Net cash + $300M FCF + Semilab + SK Hynix $240M visibility; 46x P/E demands execution
3	PDFS	3.70	WATCH → BUY ON CONFIRMATION	Best business quality (94% recurring), Kibarian alignment; gapped above PT without catalyst
4	UCTT	2.74	WATCH (starter only)	Real WFE leverage but 42x P/E on 15% GM subsystems + securities class action
5	8027.TWO	2.29	WATCH / SPECULATIVE PILOT	Priced entirely on TGV optionality; Chairman 47.9% share pledge; binary earnings

Positioning per name:

AT&S ATS (ATS.VI) — world's #5 ABF IC substrate maker (~8% global share), the only scaled European player; makes the connection layer between chip and board for AI accelerators (AMD anchor, Intel, 3 unnamed AI chipcos). The €1B Kulim, Malaysia campus is the growth asset (HVM-certified with AMD May 2025, ramping to €2.1-2.4B FY2026/27 from €1.59B). The substrate shortfall widens to 42% by 2028. Highest absolute dollar growth in the group, best PEG, earnings-driven re-rating. The "if you can only buy one" pick.
Onto Innovation ONTO — #3 process-control company; Dragonfly systems inspect advanced-packaging structures (bump heights, die alignment) that every EMIB/CoWoS/HBM line requires; Atlas handles OCD metrology for leading-edge logic. $495M Semilab acquisition (Nov 2025) adds materials characterization; SK Hynix $240M agreement through 2027. Net cash $640M, $300M FCF. Top risk: KLA encroaching on the packaging inspection niche, which would decompress the 46x multiple.
Ultra Clean Holdings UCTT — makes the precision subsystems (gas/chemical delivery, weldments, frames) inside the WFE that AMAT/LRCX/KLA ship to fabs. Extreme customer concentration (AMAT + LRCX = 57%). Runs at ~65% of $3B revenue-capable capacity, so WFE recovery flows through at ~35-40 cents per dollar — the most dramatic operating-leverage story, but on 15% gross margins, with a pending securities-fraud class action. 280% YTD move is ~65% multiple-driven (the most fragile in the group).
PDF Solutions (PDFS) — the analytics/software layer; Exensio harmonizes 50+ data formats, sells outcomes via a Gainshare model (revenue tied to customers' yield gains); Cimetrix embedded in every major OEM's SDK; secureWISE for fab connectivity. Intel publicly endorsed Exensio. 94% recurring, 76% gross margin — best business quality and best management alignment (Kibarian) in the cohort.
E&R Engineering (8027.TWO) — laser micromachining and plasma equipment for packaging; the relevant tech is TGV (Through-Glass Via) drilling for the glass-core substrates Intel is developing for EMIB-T. Pre-commercial, loss-making (~$55M revenue), priced entirely on optionality; Chairman Wang's 47.9% share pledge is a structural governance alert.

Best two-to-three combination per the showdown: ATS + PDFS + ONTO — substrate manufacturing → yield analytics → inspection, minimal overlap, differentiated risk/return. UCTT and 8027 are not additions at current prices.

European compound-semiconductor monopolists

_compare/soitec-vs-aixa-showdown pits two European mid-cap monopolists, both in cyclical troughs riding the same AI tailwinds:

Soitec (SOI) — makes the engineered substrates (SOI wafers) that go into chips via the patented Smart Cut process; 70%+ market share, 4,300+ patents, an A+ moat (the strongest in semis). Revenue split: Mobile Comms ~61%, Edge & Cloud AI ~24% (growing +27% YoY on photonics-SOI for 800G/1.6T optics), Auto & Industrial ~14%. The product is consumed, so demand is smoother than equipment. Top risk is CEO succession (Pierre Barnabé departing Mar 31, 2026, no successor named) plus the SmartSiC bet (€41M impairment). Dramatically cheaper than Aixtron — 5.8x vs. 29.7x EV/EBITDA, 1.1x book. The showdown's clear BUY (score 3.82): deeper moat, deeper trough, asymmetric entry after the €59→€44 pullback.
Aixtron AIXA — makes the MOCVD deposition systems that grow compound-semi layers (GaN, SiC, InP) atom-by-atom; 77% MOCVD share, 306 patent families, an A- moat. Segments: Power Electronics (GaN+SiC) 57%, Optoelectronics 23% (fastest-growing, G10-AsP AI-laser platform), LED/Micro LED 15%, 20% recurring service. Fortress balance sheet: zero debt, €225M net cash, ROIC above WACC even at trough — the better business. But the stock nearly 4x'd off its low to €32.60, trades at ~30x EV/EBITDA above analyst targets (~€27-28) and the deep-dive fair value (€20-22). The showdown verdict is WATCH (score 3.14): good business, bad price; limit order at €22-25.

The framing distinction: Soitec carries more business risk (CEO, deeper trough, SmartSiC), Aixtron more valuation risk (priced for perfection). For a long-term investor the moat protects against business risk; valuation risk is not protectable — which tilts the call to Soitec.

Japanese AI/optical-supercycle cohort

_compare/santec-vs-jem-vs-anritsu-and-more-versus ranks five Japanese names across the AI/semi/optical supercycle (composite scores in parentheses):

Dexerials (4980, score 4.15) — BUY. Specialty electronic materials (ACF 74% global share, anti-reflection films 93%); near-monopoly positions, 36% operating margin, 31% ROE, best-in-class capital allocation (73% total payout), cheapest at 15x forward P/E. Clear winner; main risk is geopolitical (54% revenue from China + Taiwan).
JEM (6855, score 3.60) — WATCH. Highest growth momentum (+47% revenue on HBM), reasonable 21x TTM, but cyclical and +246% in 52 weeks; wait for a deeper pullback. See 6855.
Santec (6777, score 3.10) — WATCH. Precision optical components and OCT/test instruments; A+ business (58% GM, 46% ROIC) at an F valuation (38x P/E, RSI ~98). Sell the rip, buy the dip.
Anritsu (6754, score 3.05) — PASS. Telecom T&M, industry-standard BERTWave MP2110A for 10G-1.6T optical transceiver manufacturing; good franchise but 35x P/E for ~9% growth, ROE only 7.4%; Keysight's R&D budget exceeds Anritsu's entire revenue.
Taiyo Yuden (6976, score 2.50) — PASS. Passive components (MLCCs, inductors); weakest financials, depressed margins, expensive on a normalized basis.

The recommended diversified pair is Dexerials + JEM: defensive monopoly quality plus cyclical HBM growth upside, with low business overlap.

Adjacent / not-yet-covered names

Several tickers in scope are referenced only as adjacencies or end customers and have no standalone vault treatment in these sources:

BESI BESI (BE Semiconductor) — flagged in the burn-in primer as the hybrid-bonding proxy: BESI bonding volumes are a read on 3D-IC assembly intensity, which drives KGD/burn-in demand. No dedicated page among these sources.
TXN TXN (Texas Instruments) — appears only as a customer/IDM in the probe-card supply chain, not as an analyzed equipment play.
TEL TEL (Tokyo Electron, 8035) — the wafer-prober and broad fab-equipment giant; appears as a Stage-2 prober supplier and in the master-FAQ peer list (alongside ASML, AMAT, KLAC, LRCX). No deep dive in these sources.
CAMT (Camtek), TSEM (Tower Semiconductor), AXTI (AXT Inc), 6451 — listed as in-scope tickers for this section but NOT covered in any of the read source files. They likely have their own ticker pages or belong to other sector pages; flagged here so the gap is explicit rather than silently dropped.

Monitor

A rolling log of dated developments, scheduled catalysts, earnings checkpoints, and standing watch-items for the semiconductor capital equipment and test sector. This is the living section: dated specifics belong here with their dates, and the standing checklist at the bottom is what to re-check every cycle. Company-specific theses live on the ticker pages; this section tracks the events and signals that move the whole test/inspection/metrology complex.

Dated developments and policy moves

Events below are sourced from the underlying primers and showdowns, carrying their original dates. Read them as a timeline of what has already happened and shaped the current setup.

2024-10-08 — TSMC publishes its 2nm CMOS logic platform technical paper (GAA nanosheet architecture). Every GAA transition raises metrology intensity per wafer step (channel thickness, composition, strain across stacked sheets) — direct read-through to HRXRD and CD-SAXS demand. See tsmc-2nm-platform.
2024-10-09 — Carlyle-backed Rigaku (268A) sets tentative IPO price at JPY 1,230-1,260 per share.
2024 (FY) — FormFactor (FORM) HBM revenue quadrupled in 2024; $764M FY2024 revenue (+15% YoY). HBM now ~half of DRAM revenue (~15% of total company revenue); ships to all three HBM makers (Samsung, SK Hynix, Micron).
2024-11 (Malvern Panalytical) — Acquired Freiberg Instruments XRD products; expanding into semiconductor metrology, entering the Rigaku/Bruker duopoly.
2025-05 — AT&S Kulim (Malaysia) achieves HVM certification with AMD; ramping into FY2026/27 €2.1-2.4B guided revenue. See ATS.VI.
2025-06 — AT&S Leoben HTB3 facility opened (EU Chips Act); targeting 20,000 panels/month by 2027. Rigaku (268A) expands production facilities for the semiconductor market (BusinessWire, 2025-06-26).
2025-07 — AEM Holdings (AWX) installs new CEO Kabbani (3rd CEO in 2 years).
2025-09 — Technoprobe opens EUR 80M Dresden MEMS facility; won 30% of TSMC 2nm probe-card qualifications. Teradyne invested $516M in Technoprobe.
2025-11 — Onto Innovation (ONTO) closes $495M Semilab acquisition (materials characterization); cash from $852M → $640M, no debt added. Expected to contribute $100-120M incremental revenue, H2-weighted FY2026.
2025 (PDFS) — PDF Solutions (PDFS) acquires secureWISE (~$130M); Intel publicly endorses Exensio and licenses Tiber AI Studio to power Exensio Studio AI.
2025-12-16 — Rigaku launches ONYX 3200, an X-ray metrology instrument for advanced packaging / HBM micro-bump and Cu-pillar measurement (BusinessWire). See xray-semi-metrology-primer.
2025 (FY) — Test equipment spending surged 48.1% in 2025, driven by complex AI architectures. Samsung and SK Hynix shipped >250M HBM stacks in 2025. SK Hynix sold out its entire 2026 HBM supply. TSE probe-card revenue +90% YoY in 2025.
2025-Q4 — E&R Engineering (8027.TWO) posts first operating-profitable quarter in five quarters: TWD 66M op. profit on TWD 721M revenue (+67% YoY). Open question on whether this is a run-rate or one-quarter AIS recognition event.
2026-01 — Aixtron (AIXA) announces headcount reductions (proactive cost-cutting through the downcycle).
2026-02-25 — AEM Holdings (AWX) FY2025 press release; FY2025 revenue S$399M (+5%), guidance S$460-510M FY2026 (+15-28%).
2026-03 — Soitec (SOI) Skyworks multi-year POI supply agreement (validates product; 11 customers in production, 13+ qualifying). CEO Pierre Barnabé departing 2026-03-31, no successor named (key-person risk flag).
2026-03-13 — Sunright (S71) 1H FY2026 results; revenue inflecting (+15% in 1H), approaching the ~S$85M operating breakeven threshold.

Earnings checkpoints and forward catalyst calendar

The single most catalyst-dense window is late April through May 2026, when most of the test/packaging supply-chain names report. Treat each as a thesis-confirm-or-break gate.

Date	Name	Event	Why it matters
Apr 28, 2026	UCTT (UCTT)	Q1 2026 earnings	Binary: H2 2026 WFE demand guidance confirmation or thesis delay; ~65% of 280% YTD move was multiple-driven, most fragile in the group
Apr 28, 2026	DELTA.BK	Q1 earnings	AI server PSU context for broader advanced packaging thesis
Apr 30, 2026	2308/2308	2308.TW (Delta Taiwan)	Q1 earnings
Apr 30, 2026	Aixtron (AIXA)	Q1 2026 results	At 43x trailing / 30x EV/EBITDA, little margin for error; SiC overcapacity clearing pace
May 7, 2026	PDFS (PDFS)	Q1 FY2026 earnings	First confirmation of Gainshare Intel 18A yield-ramp contribution
May 2026	ATS.VI (ATS.VI)	FY2025/26 full-year results	Revenue €1.7B+ and EBITDA margin ≥22% = all-clear for FY2026/27 entry; miss = thesis reset
May 11, 2026	AEM Holdings (AWX)	Q1/earnings	First major test of the unnamed AI/HPC customer ramp; overbought into print (RSI 80.7)
May 11, 2026	E&R Engineering (8027.TWO)	Q1 2026 (TWO) earnings	Pivotal binary: is Q4 2025's TWD 721M a run-rate or a one-quarter AIS event? Step-down to TWD 300-400M retests TWD 100
Jun 5, 2026	Sunright (S71)	Earnings	Watch for revenue crossing the ~S$85M operating-breakeven threshold
Q2-Q3 2026	ATS.VI (ATS.VI)	EU Chips Act Leoben expansion milestone	20,000 panels/month by 2027 = third growth engine beyond Kulim
2H 2026	Intel EMIB-T ramp	Multi-company	Advanced packaging >$1B annual Intel commitment; external customers begin prepaying; ATS.VI, ONTO, 8027.TWO all have direct exposure

Burn-in / WLBI cycle indicators

The wafer-level burn-in segment (AEHR, burn-in-test-primer) follows the HBM capex cycle more than the commodity DRAM/NAND cycle. The current period (2025-2026) is the re-entry window after the 2023-2024 SiC-driven drawdown, with HBM3e capacity investments accelerating at all three DRAM makers, Intel 18A approaching volume, and chiplet architectures ramping.

Standing leading indicators to track:

SK Hynix HBM capacity guidance and WaferPak order disclosures
Aehr FOX-XP backlog (quarterly earnings, direct WaferPak order disclosure)
Memory capex from SK Hynix / Samsung / Micron (6-12 month leading indicator for FOX-XP orders)
Micron HBM share gains — Micron is more transparent about Aehr adoption; track its HBM capex
Intel 18A production yield disclosures (and whether glass-core chiplet assembly mandates WLBI / DiePak)
Aehr DiePak first production customer win — the catalyst to re-rate Aehr as an advanced-packaging play
SiC wafer-start guidance from Onsemi / Wolfspeed / STMicro — leading indicator for Aehr SiC WaferPak orders and for 2360 (Chroma) power burn-in
BESI hybrid-bonding volumes as a proxy for 3D-IC assembly intensity driving KGD demand

The capex chain to follow: NVIDIA $100B+ AI infra, Microsoft $80B, Meta $40B → SK Hynix/Samsung/Micron HBM ramp → Aehr FOX-XP orders (6-12 month lag) → WaferPak replacement cycle (continuous). The second-derivative pattern is that the WaferPak consumable stream — not the system order — is the compounding leg that arrives 12-18 months after system installation. Most models do not break this out; if SK Hynix runs 500+ HBM wafer-starts/day, monthly WaferPak consumption could imply $200-400M/year TAM by 2027.

Probe card and metrology demand signals

Probe card demand (semi-probe-card-primer) is consumable and design-cycle-driven: it compounds with both wafer volume and design complexity/diversity. The market declined ~18% in 2023 (memory downturn), then rebounded sharply in 2024-2025. Things to watch:

HBM stack-height progression (8-high → 12-high → 16-high) — each generation multiplies TSV connections to test and forces new probe-card designs. BofA estimates the HBM market reaches $54.6B in 2026 (+58% YoY), ~600% cumulative growth to 2030.
FormFactor / Technoprobe / MJC HBM revenue mix as the cleanest read on advanced-node test intensity
TSMC 2nm probe-card qualification share (Technoprobe took 30%) — leading edge MEMS displacing cantilever
Whether JEM (6855) can demonstrate credible MEMS/vertical capability vs. its cantilever heritage — the single most important watch-item on that name
Japan's JPY 2T ($13.4B) domestic fab allocation creating local-sourcing demand for JEM and MJC
CoWoS capacity (sold out through 2026) as a proxy for advanced-packaging KGD test demand

On the metrology side (xray-semi-metrology-primer): Rigaku's semiconductor process-control segment grew ~20% in FY2025, implying the semiconductor X-ray metrology sub-segment is running 15-25% CAGR vs. 3-5% for the broader analytical-instruments market. Watch GAA 2nm ramp (Atlas G6 / HRXRD upgrade cycle), 3D NAND layer counts (200-300+), and the pace of compact high-brilliance X-ray source development — if sources don't improve fast enough, CD-SAXS may not hit inline throughput for HVM.

Standing watch-items / cross-cycle checklist

Re-check these every reporting cycle regardless of headlines:

Semiconductor cyclicality. Semicap spending runs 2-3 year boom/bust cycles; metrology and probe-card orders correlate with fab construction and node transitions. Service/parts/consumable revenue provides a partial buffer. Memory cycles are the most volatile leg.
Export controls. US/Dutch/Japanese controls on advanced equipment to China cover metrology tools; FormFactor already restricted on advanced probe cards to China. Burn-in equipment not yet restricted (flag, not near-term). Watch any tightening that shrinks the China-addressable market for Rigaku, FormFactor, and others.
Advantest WLBI entry. Does Advantest (6857) have a commercial wafer-level burn-in roadmap? This is the most serious competitive risk to AEHR — confirmation or denial materially updates the thesis. No timeline confirmed.
Customer concentration. A handful of leading-edge fabs (TSMC, Samsung, Intel, SK Hynix, Micron, KIOXIA) drive the whole metrology/test demand pool; loss of one, or one fab switching vendors, has outsized impact. Same dynamic on probe cards (TSMC for logic; Samsung/SK Hynix/Micron for memory) and on equipment names with single-anchor exposure (AEM/Intel >50%; ATS.VI/AMD).
KLA encroachment into packaging inspection. Onto's (ONTO) OCD share has already slipped vs. KLA; if packaging inspection follows OCD toward KLA, Onto's premium multiple decompresses. Watch competitive wins on EMIB/CoWoS/HBM inspection lines.
Technology displacement in metrology. E-beam (AMAT PROVision), AI-enhanced optical, and hybrid approaches compete for the same process-control budget. Track whether X-ray gains or stalls at advanced nodes.
Chinese domestic entrants. Hangzhou Changchuan (burn-in, commodity), MaxOne/Shanghai Zenfocus/JUNR (probe cards, ~2% share), and domestic metrology efforts compete on price and delivery; CXMT's advanced-DRAM ambitions are the long-term open question for China sourcing.
MEMS lifetime headwind. Longer probe-card life (10M+ touchdowns) and self-cleaning tech (MPI ultrasonic, +50% life) reduce replacement unit volumes even as ASPs rise. Net effect on unit demand is the thing to monitor.
WaferPak contact-life improvement. Gradual headwind to Aehr's consumable intensity — track whether contact life rising offsets wafer-volume growth.
SiC / EV demand. SiC burn-in (Aehr, Chroma) and SiC equipment (Aixtron) depend on EV adoption running below prior expectations; SiC overcapacity clearing (Aixtron expects ~2027) is a dated watch-item.
Tariffs / FX. Rigaku runs 69% overseas revenue; JPY/USD exposure across the Japanese names (Advantest, JEM, MJC, Yamaichi); universal tariffs raise cross-border equipment costs.

Open research questions (carried, unresolved)

WaferPak per-wafer economics at production scale — actual revenue-per-wafer from replacements at a major HBM fab.
Advantest commercial WLBI product timeline.
Intel 18A burn-in specification — does glass-core chiplet assembly mandate WLBI / DiePak?
Micron HBM share gains and capex trajectory as a leading indicator for new Aehr customer ramp.
3D-IC stack burn-in (R&D at IMEC and national labs) — if mature, adds a burn-in step to the advanced-packaging flow (3-5 year horizon).
Integrated ATE + burn-in (Advantest working on ATE-vector-driven burn-in) — would commoditize standalone package-level ovens but not wafer-level physics.

Cross-references

burn-in-test-primer — WLBI cycle positioning, leading indicators, open questions (full treatment)
semi-test-supply-chain — full stage map (Stage 1 metrology → Stage 5 SLT)
semi-probe-card-primer — probe-card demand drivers and risks
xray-semi-metrology-primer — X-ray metrology growth drivers and risks
AEHR, FORM, 6855, 268A, ONTO, ATS.VI, PDFS, UCTT, 8027.TWO, AWX, S71, SOI, AIXA, 6857, 2360 — ticker pages

Sources

The semicap test and metrology research in this sector draws on a mix of independent analysts (mostly Substack and X), sell-side and market-research houses, company IR and technical disclosures, and a handful of standards and reference works. Where an author or publication has a profile page under _sources/, it is linked below; the rest are external references cited inline in the underlying notes.

Independent analysts and Substacks

source-damnang — Damnang (@damnang2, Substack). Cited directly in the burn-in primer for "Why AEHR Matters Right Now" — the source for the WaferPak-consumable-as-compounding-leg thesis. In the AEHR inv-q queue. EE PhD; deep technical semiconductor research (photonics, HBM, CPO, hybrid bonding).
source-semianalysis — SemiAnalysis (Dylan Patel et al., paid). Cited for HBM architecture analysis in the burn-in primer; the master-faq flags the "Semi Analysis packaging series" on the HBM / hybrid bonding / DRAM relationship as a research target. Recommended for the SK Hynix / Samsung / Micron memory-capex read-through.
Dr. Robert Castellano (Castellano, Substack — "KLA's Market Share Growth in Process Control") — primary cited source for KLA's ~55-63% process-control share in the X-ray metrology primer.
iamfabian (Substack — "Anritsu: The Quiet Japanese Giant") — Anritsu deep-dive cited in the Santec/JEM/Anritsu/Taiyo Yuden/Dexerials showdown.
Mark Lapedus / Semi Ecosystem (Substack — "Test Challenges Grow for DRAMs and HBM") — DRAM/HBM test difficulty, cited in the probe-card primer.
TSPA Semiconductor (Substack) — "IC Testing: A Comprehensive Analysis" and "Advantest Leading the AI Testing Wave," cited in the probe-card primer.
Chips and Wafers (Substack — "Semiconductor Test: A Compelling Investment Theme") — cited in the probe-card primer.

These Substack/X analysts are the DEFAULT research inputs per Pink's standing rule; press-release-only coverage is treated as insufficient.

Sell-side, exchanges and market-data

BofA (Bank of America) — HBM market sizing: $54.6B in 2026 (+58% YoY), 600% cumulative growth to 2030. Cited in both the probe-card primer and master-faq context.
TrendForce — HBM prices 2025.
The Next Platform — "HBM Supply Curve Gets Steeper But Still Can't Meet Demand."
The Elec — TSE HBM probe-card supply reporting.
JW Insights (ijiwei) — China probe-card market.
The Worldfolio — Korea Instrument global probe-card strategy interview.
Rosenblatt, DA Davidson — analyst PT revisions cited in the ATS/ONTO/UCTT/PDFS/8027 showdown (ONTO and PDFS price targets).
Yahoo Finance, stockanalysis.com, MarketScreener, Simply Wall St, TradingView, Stockopedia, TipRanks, Alpha Spread, Omega Investment, stockopedia.com — quote/financials/technical data feeds across the four showdown notes (Japanese tech five-way; SOI vs AIXA; AWX vs S71; ATS/ONTO/UCTT/PDFS/8027). SGX filings used for the Singapore burn-in pair.

Market-research / TAM houses (X-ray metrology and probe-card primers)

Business Research Insights — X-Ray Diffraction Instrument Market.
Global Growth Insights — XRD/XRF Instrument Market; XRD Machines Market competitive landscape.
SNS Insider — X-Ray Fluorescence Analyzer Market.
Fortune Business Insights — Semiconductor Metrology and Inspection Equipment Market.
Straits Research — Semiconductor Metrology and Inspection Equipment Market.
Strategic Market Research — Probe Card Market ($3.31B by 2030, 7.9% CAGR).
Intel Market Research — Semiconductor Probe Cards Outlook ($2.4B → $3.6B by 2032, 5.8%).
QY Research — Probe Card Market ($2.6B → $3.9B by 2031, 5.4%).
Mordor Intelligence — Probe Card Market ($2.7B 2026 → $4.2B by 2031, 9.3%); cited in both the probe-card primer and the Japanese five-way showdown.
Technavio — Probe Card Market (9.4% CAGR 2024-29).
Stellarm Research (Stellar Market Research) — Probe Card Market 2025-2032.

Company / institutional primary sources

TSMC — "TSMC's New, Industry-Leading 2nm CMOS Logic Platform" technical paper (Oct 8, 2024); the tsmc-2nm-platform note. Anchors the GAA/2nm metrology-intensity and probe-card qualification narratives (Technoprobe's 30% of TSMC 2nm qualification wins).
Rigaku (268A) — Medium-Term Business Plan (Feb 2025), Integrated Report 2025, ONYX 3200 launch (BusinessWire), production-facility expansion (BusinessWire), Carlyle-backed IPO pricing (US News), semiconductor-metrology division pages. Primary source for XRD share (~26-29%) and the inline XTRAIA product family.
Bruker (BRKR) — X-ray metrology for silicon semi product pages, "How does XRF work," FY2024 results (Yahoo Finance).
Malvern Panalytical (Spectris) — semiconductor-metrology acquisition press releases (Freiberg Instruments XRD).
FormFactor (FORM) — multiple corporate blog/IR items: MEMS vs traditional probe cards, HBM testing video, wafer-test challenges, high-speed memory/KGD test, advanced-packaging test, Q4 2024 and Q2 2025 earnings.
Technoprobe — "What Is a Probe Card" page and CMD 2025 capital-markets presentation.
Micronics Japan / MJC (6871) — Medium-Term Business Plan FV26.
MPI Corporation — 2024 investor presentation (self-cleaning tip tech).
JUNR / Wuxi Junr — "Top 10 Probe Card Manufacturers 2025" blog.
SK Hynix — "2026 Market Outlook: HBM-led Memory Supercycle."
Anritsu IR (financial strategy); Dexerials IR (market share); Taiyo Yuden IR — used in the Japanese five-way showdown.
Soitec IR and Aixtron IR (investor pages, FY2025 results, H1/Q3 FY26 reports) — the SOI vs AIXA showdown.
AEM FY2025 press release (Feb 25, 2026) and Sunright 1H FY2026 results (Mar 13, 2026) — the AWX vs S71 burn-in showdown.
Vault deep-dive pages used as the primary input for the showdowns: ATS.VI / ONTO / UCTT / PDFS / 8027.TWO (all 2026-04-26), AWX / S71 (2026-04-26), and the Japanese five (6777 / 6855 / 6754 / 6976 / 4980).

Standards, government and reference

JEDEC standards — JESD-35 (voltage acceleration), JESD22-A108 (burn-in stress test), JESD47 (IC qualification); AEC-Q100 (automotive, Grade 0/1 0-DPM screening). Foundational to the burn-in primer.
NIST — CD-SAXS program (origin of the critical-dimension small-angle X-ray scattering technique now being commercialized).
Congress.gov / CRS — "U.S. Export Controls on Semiconductors" (R48642), cited on the China/export-control risk in the X-ray metrology primer.
Dragonfly / Comet — "High-Resolution 3D X-ray Inspection for Advanced Packaging" (HBM micro-bump analysis).
Semiconductor Engineering — "3D Metrology Meets Its Match in 3D Chips and Packages" and "Metrology Digs Deep to Produce Next-Generation 3D NAND."
Wikipedia — X-ray Fluorescence, Rigaku, Probe Card, Wafer Testing.
Wevolver — "Wafer Probing: An Ultimate Guide"; Tektronix — Probe Card Tutorial; Venture MFG — "Cantilever vs Vertical Probe Card."
IMEC — referenced (master-faq, burn-in primer) as the Belgium-based transistor-scaling research house near ASML; flagged for BSPDN performance-advantage work and 3D-IC stack burn-in R&D.

Consolidated source files (the underlying notes for this sector)

burn-in-test-primer — KB/wiki/themes/burn-in-test-primer.md
xray-semi-metrology-primer — KB/wiki/xray-semi-metrology-primer.md
semi-probe-card-primer — KB/wiki/semi-probe-card-primer.md
semi-test-supply-chain — KB/wiki/semi-test-supply-chain.md
master-faq — KB/wiki/master-faq.md (cross-cutting semi questions/notes; the "Semi Analysis packaging series" and IMEC/BSPDN research pointers live here)
universal-notes — KB/wiki/universal-notes.md (stub — "to be populated"; no content yet)
ats-vs-onto-vs-uctt-and-more-showdown — KB/wiki/_compare/ats-vs-onto-vs-uctt-and-more-showdown.md
awx-vs-s71-showdown — KB/wiki/_compare/awx-vs-s71-showdown.md
santec-vs-jem-vs-anritsu-and-more-versus — KB/wiki/_compare/santec-vs-jem-vs-anritsu-and-more-versus.md
soitec-vs-aixa-showdown — KB/wiki/_compare/soitec-vs-aixa-showdown.md
tsmc-2nm-platform — KB/wiki/tsmc-2nm-platform.md

Open source-gathering notes

The burn-in primer's best-sources list flags two items not yet captured as standalone source pages: Aehr quarterly earnings transcripts (the only direct WaferPak-order disclosure) and SK Hynix / Samsung / Micron memory-capex guidance (the 6-12 month leading indicator for WLBI orders). The master-faq remains a research backlog rather than a finished note — its IMEC/BSPDN and SemiAnalysis-packaging-series pointers are unresolved threads, not citations.

Consolidation queue (merged 2026-05-30 — section-scoped rebuild)

Industry-wide content folded in from these source files. They stay live pending Pink's archive confirm.

[ ] themes/burn-in-test-primer.md
[ ] xray-semi-metrology-primer.md
[ ] semi-probe-card-primer.md
[ ] semi-test-supply-chain.md
[ ] master-faq.md
[ ] universal-notes.md
[ ] _compare/ats-vs-onto-vs-uctt-and-more-showdown.md
[ ] _compare/awx-vs-s71-showdown.md
[ ] _compare/santec-vs-jem-vs-anritsu-and-more-versus.md
[ ] _compare/soitec-vs-aixa-showdown.md
[ ] tsmc-2nm-platform.md

Pages that link here (6)

8027 — E&R Engineering Corporation AWX — AEM Holdings Ltd ONTO — Onto Innovation Inc.S71 — Sunright Limited (SGX: S71)UCTT — Ultra Clean Holdings, Inc.AIXTRON SE (AIXA) - Comprehensive Stock Pitch

Open in Obsidian