Memory

Overview / thesis

Memory is breaking out of its 35-year identity as a commodity cycle stock — "build fab, oversupply, lose money, capacity rationalizes, supercycle, repeat" — and the 2025-2026 cycle is structurally unlike anything in the industry's history. Three forces collide at once: (1) AI inference demands HBM bandwidth at a magnitude no roadmap anticipated; (2) the NAND industry exits sub-32GB MLC just as KV-cache offloading creates a new structural demand category; and (3) China's domestic build-out (CXMT in DRAM, YMTC in NAND) accelerates while remaining 2-3 nodes behind. The result: SK Hynix posted a 49% operating margin in FY2025 (an all-time record for any memory maker, 72% in Q1 2026), Micron roughly tripled revenue inside 18 months, Macronix re-rated ~350-844% on an eMMC-monopoly thesis, and Kioxia compounded ~24x off its IPO price (¥1,455 → ¥34,580).

Quantified TAM

Segment	2025 TAM (USD)	2030 TAM est. (USD)	CAGR
Total memory market	$180B	$310-350B	11-14%
DRAM	$108B	$190B	12%
of which HBM	~$30B	$130B+	~34%
of which DDR5 (server)	$50B	$90B	12%
of which LPDDR (mobile)	$25B	$40B	10%
NAND	$65B	$115B	12%
of which enterprise SSD	$25B	$55B	17%
of which client SSD	$20B	$30B	8%
of which mobile (UFS/eMMC)	$15B	$20B	6%
of which industrial/auto	$5B	$10B	14%
NOR	$4-5B	$10-11B	8%
HDD (high-cap nearline)	$20B	$25B	5%

The single most important number: HBM is growing ~3x the speed of the broader memory market (~34% CAGR vs ~11-14%). By 2030, HBM alone (~$130B+) is projected to approach the size of the entire DRAM market today (~$108B). Despite riding on only ~5-8% of total DRAM bits, HBM already captures roughly 20-30%+ of DRAM revenue and profit — the clearest signal that value has decoupled from volume. (SK Hynix specifics: HBM was 30% of DRAM revenue in Q3 2024, >40% by Q4 2024.) NOR market sizing varies by scope: Custom Market Insights puts 2024 at $3.0B → $10.7B by 2034 (8.2% CAGR); Technavio/Mordor put it nearer $4.9-5.5B; consensus is ~$4-5B for serial+parallel combined.

The commodity-vs-specialty split

The core structural insight is that memory has bifurcated into two businesses with opposite economics:

• Commodity tier — standard DDR5/DDR4 server/PC DRAM, mainstream TLC/QLC NAND. Historically priced spot or quarterly, supplier-switchable, exposed to the classic cycle, and the segment where Chinese capacity (CXMT, YMTC) substitutes most readily.
• Specialty / contracted tier — HBM, plus specialty memory (NOR, low-density/specialty DRAM, sub-32GB eMMC). HBM is sold under multi-year contracts to NVIDIA, AMD, and hyperscalers; capacity is sold out 18 months forward; pricing is sticky; margins are 60%+. SK Hynix's record FY2025 was driven by HBM3E shipments to NVIDIA Blackwell, not a commodity DRAM up-cycle — closer to the TSMC business model than the historical Samsung Memory model. There is no HBM spot market: every wafer is spoken for.

This split is reinforced by an emerging "durability debate": SK Hynix, Samsung, Micron and SanDisk have all signed multi-year customer supply agreements with prepayments (10-30% of contract value, up from <5% historically), minimum price guarantees, and walkaway penalties. SanDisk's Q3 FY26 disclosure crystallized it — 5 "New Business Model" (NBM) agreements, ~$42B minimum contractual revenue from 3 of them, >$11B aggregate financial guarantees, and >1/3 of FY27 bits locked. SemiConSam frames the chicken-game era as structurally over: after three consolidation rounds (Qimonda bankruptcy 2009, Elpida bankruptcy 2012, Micron's rolling acquisitions), only the Big 3 remain in DRAM, further consolidation is politically/antitrust-blocked, and HBM is becoming "foundry-like" via custom HBM (cHBM). The open question — is memory still cyclical? — is the single most important investment question in the sector. The market's answer is mixed: SNDK actually fell on its blockbuster Q3 FY26 print as investors debated whether fixed-price NBMs cap upside or signal structural multi-year demand.

The investable 2025-2027 thesis

FundaAI, SemiAnalysis, and Irrational Analysis converge on a 2027-2028 supply-tightness thesis: the capex needed to relieve current shortages does not deliver wafer output until late 2027 at the earliest. This is a multi-year up-cycle, not a quarter-to-quarter print. Cycle position as of April 2026: DRAM contract prices +58-63% QoQ and NAND +70-75% QoQ (Q1/Q2 2026); HBM bookings sold out through CY2026 and much of 2027; customer inventory below normal; capex disciplined (+5% in 2026 — Micron $25B, focused on node transitions and hybrid bonding, not greenfield wafers); wafer capacity cut 10-15% from peak; sell-side models show DRAM shortage through 2027 and NAND shortage through 2028. NAND bit demand is growing 20-22% against 15-17% bit supply. This is the most cycle-favorable setup for memory equities since 2017-2018.

Where to look (from the primer's TL;DR):

• Tier 1 conviction — SK Hynix (HBM near-monopoly, ~62% share), Micron (HBM share gainer, 21→24%), Macronix (sub-32GB eMMC monopoly post-2028).
• Tier 2 tactical — Kioxia (NAND pure-play, but Bain selldown overhang), SanDisk (post-spin operating leverage), Samsung (HBM3E qualification recovery story).
• Watchlist — Winbond (specialty DRAM scarcity, sold out through 2027), Montage (DDR5 RCD), Rambus (memory IP), AEHR (HBM wafer-level burn-in).
• Avoid — Western Digital legacy HDD without a HAMR catalyst; commodity DDR4 specialists exposed to China substitution.

Market structure and where value accrues

Memory is the highest-operating-leverage business in semis: fixed costs are 70-80% of total, so every dollar of incremental ASP drops nearly straight to gross margin. The Sandisk gross-margin trajectory (29.9% → 51.1% → 65-67% guided across three quarters) is the most extreme operating-leverage move in memory history.

The supply side is concentrated and getting more so. DRAM: 3 players (Samsung, SK Hynix, Micron) control >95% globally; SK Hynix surpassed Samsung as #1 DRAM revenue in 2025 for the first time (Counterpoint 2025 revenue share: SK Hynix 35%, Samsung 34% — down 7pp on the HBM3E qualification miss — Micron 24%, CXMT 5% doubled from 4%). NAND: 6 players, fragmenting (Counterpoint 2025: Samsung 30%, Kioxia 16%, Micron 13%, SanDisk 12%, SK Hynix 11%, YMTC 10% up from 7% despite the 2022 Entity List, Solidigm 8%). YMTC's +3pp NAND gain is the most concerning datapoint in the complex for the durability thesis.

Value pools sit at two layers above the IDMs and one to the side:

• Memory IDMs (HBM premium) capture the largest share this cycle — 40-50% peak gross margins on DRAM, the HBM contract premium driving the record results.
• HBM packaging (TSMC CoWoS) is the chokepoint — TSMC holds ~85% of HBM CoWoS at 55-65% gross margins; Samsung a distant second. Wafer-bonding capacity takes 18-24 months to build.
• Memory IP & DDR5 RCD chips earn the highest margins (60-75%) on small revenue — Montage (36.8% DDR5 RCD share), Renesas, Rambus — high-quality compounding exposure (every registered server DIMM needs an RCD).
• Specialty memory (Winbond, Macronix, Infineon, GigaDevice) at 30-45% margins, protected by automotive ASIL-D qualification switching costs.
• Module assembly (Kingston private, Crucial/Micron, ADATA, Patriot) is the value sink at 5-15% margins.

A geopolitical layer overlays everything: memory is now a strategic resource governed by industrial policy. YMTC is on the US Entity List (Dec 2022; DoD "military company" designation Feb 2024); CXMT is the next sanctions-candidate; CHIPS Act provides $39B in grants (Micron $6.1B, Samsung $6.4B, TSMC $6.6B); China's Big Fund III ($47B) backs CXMT and YMTC. The structural edge: China-domestic memory substitutes for low-end DDR4/DDR3 and 2D NAND but cannot yet substitute for HBM (3+ generations behind), advanced DDR5 (1-2 behind), or sub-32GB MLC eMMC (no credible substitute) — the underpinning of the SK Hynix and Macronix theses.

How it works

Computers compute by moving bits between transistors; storage is the problem of holding bits between operations across timescales from nanoseconds (registers) to decades (archival). The fundamental tension is that no single physical mechanism can be simultaneously fast, dense, and cheap — this is not an engineering failure but a consequence of transistor physics, signal propagation, and thermodynamics. The industry's entire structure follows from solving this tradeoff by tiering.

The memory wall — quantified

The central problem AI has exposed is a growing imbalance between compute and the memory that feeds it. Over roughly the last 20 years, compute scaled ~60,000x while memory bandwidth grew only ~100x. Within the GPU era the same asymmetry holds at a finer grain: NVIDIA GPU floating-point performance grew ~80x from 2012 to 2022, but HBM bandwidth grew only ~17x. That gap is the "memory wall." It means modern accelerators can do arithmetic far faster than they can be fed data, so for an expanding class of workloads the bottleneck is not FLOPs but the bandwidth and capacity of memory. SemiAnalysis frames its HBM roadmap work explicitly as "Scaling the Memory Wall."

The hierarchy and locality of reference

Because no single tier wins on all three axes, modern computing stacks 8-10 tiers as concentric rings around the CPU — each larger but slower. The canonical ordering runs SRAM (caches) → DRAM (main memory) → NAND (SSD) → disk (HDD) → tape, spanning roughly ten orders of magnitude in latency (~0.3 ns for registers to ~100 seconds for tape — about 10 billion to 1) and roughly eight orders of magnitude in cost (~$12,500/GB for SRAM die area down to ~$0.005/GB for tape — about 2 billion to 1).

Tier	Latency	Cost/GB (2025)	Volatile?
CPU registers	~0.3 ns	embedded	Yes
L1 cache (SRAM)	~1 ns	~$12,500	Yes
L2 cache (SRAM)	~4 ns	~$12,500	Yes
L3 cache (SRAM)	~10-20 ns	embedded	Yes
HBM3e (on GPU)	~10-30 ns	$25-50	Yes
DDR5 DRAM	~80 ns	$3-8	Yes
CXL memory	~150-500 ns	$1-5	Mostly
NVMe SSD	~10-20 µs	$0.07-0.30	No
Enterprise HDD	~8-12 ms	$0.01-0.02	No
LTO tape	~45-100 s	$0.004-0.007	No

What makes a tiered system work — rather than just being a list of compromises — is locality of reference, the empirical fact that real programs do not access data uniformly at random. Temporal locality: recently accessed data is likely accessed again soon (a loop counter read every iteration). Spatial locality: data near a recently accessed address is likely needed next (iterating an array stored contiguously). These patterns emerge from how programs are written — loops dominate runtime, functions cluster local variables on the stack, data structures store related elements together. The consequence is decisive: a tiny cache holding 1-5% of total data can serve 80-95% of all accesses. This is the magic that makes the hierarchy economically viable. The Average Memory Access Time formula — AMAT = Hit Time + (Miss Rate × Miss Penalty) — shows a 95% L1 hit rate with a 100 ns miss penalty yields an effective ~6 ns, barely slower than pure SRAM while providing DRAM-scale capacity behind it. Without locality, you would need everything in the fastest tier: filling a server with 512 GB of SRAM would cost ~$2.5M versus ~$1,500 in DRAM, a ~1,700x difference; a 10,000-server data center would pay ~$25B for memory alone.

Why each tier exists — the cell mechanisms

SRAM stores a bit in a 6-transistor cell: two cross-coupled inverters lock the bit in a stable state plus two access transistors gate reads/writes. No refresh, no destructive read, no wear, and ~1 ns reads because the signal is strong and reading does not disturb the value. The cost is area — roughly 120 F² per cell (vs DRAM's ~6F²). Multi-gigabyte SRAM arrays would consume gigawatts of standby leakage, so SRAM is reserved for CPU L1/L2/L3 and on-die GPU memory (an H100 has 50 MB L2 and 228 MB shared SRAM across 132 SMs; AMD's 3D V-Cache reaches 1.15 GB via TSVs).

DRAM is the density breakthrough. In 1966, IBM's Robert Dennard invented the modern DRAM cell: one transistor + one capacitor (1T1C). The capacitor holds charge for a 1 (or no charge for a 0), dropping cell area to ~6 F² — roughly 20x denser than SRAM's ~120 F². Three physical properties define DRAM and flow directly from that capacitor:

1. Refresh / volatility — capacitors leak, so every ~64 ms all rows must be read and rewritten, consuming ~5-7% of memory bandwidth; cut power and all data is lost (volatile).
2. Destructive read — sensing the tiny stored charge depletes the capacitor, so the sense amplifier must immediately write the data back.
3. Off-die latency — DRAM chips sit on DIMMs centimeters from the CPU; at 5 GHz light travels only ~6 cm per clock cycle in vacuum (~4 cm on copper), so a round trip is physically too long to finish in one cycle. Latency is ~60-100 ns — roughly 300-500 wasted CPU cycles per access.

DRAM variants tune the same 1T1C cell for different ends: DDR (server/desktop, latency-optimized), LPDDR (mobile, power-optimized, <2W idle), GDDR (graphics, throughput-optimized), and HBM — which is literally DRAM (1T1C cells, same as DDR5) stacked vertically (8/12/16 dies) with Through-Silicon Vias and microbumps, sitting on a silicon interposer next to the GPU via TSMC CoWoS. The packaging, not the cell, is what makes HBM special: a 1024-bit-wide bus per stack at modest clocks delivers enormous bandwidth at low power (HBM3e: 8-9.6 Gbps, 1.0-1.2 TB/s per stack; a B200 carries 192 GB across 8 stacks for 8.0 TB/s).

NAND flash pushes density further with a single transistor whose "floating gate" traps electrons behind an oxide barrier — non-volatile, no power needed to retain. Writing forces electrons through the oxide (~20V, channel hot-electron injection), a violent act that degrades the tunnel oxide and limits endurance (~100,000 P/E cycles for SLC down to <100 for experimental PLC). Cell area drops to ~4 F², and 3D NAND now stacks 200-330+ layers, but writes take microseconds, erases happen in large blocks, and NAND is ~1,000x slower than DRAM. Below NAND, HDDs and tape abandon transistors for magnetic media, trading density for mechanical motion (milliseconds to seconds). The unifying principle: smaller, simpler cells pack more bits per unit area but require more time, more voltage, or mechanical motion to access — and heat compounds it, since 6 transistors where 1 would do means ~6x more switching energy.

Why AI workloads are memory-bound

Transformer inference makes the memory wall the binding constraint. In attention, each new token must attend to all previous tokens; without caching this means recomputing keys (K) and values (V) for the entire context at every step — quadratic in sequence length. The KV cache stores K and V from the prefill phase so decode becomes roughly linear, but at a steep memory price: KV size = 2 × layers × heads × head_dim × seq_len × bytes_per_value. For Llama 3 70B at 128K context in float16 that is ~40-42 GB per single user session — more than the entire 80 GB HBM of an A100/H100 once model weights (140 GB FP32 / 70 GB FP16) and activations are added. The decode phase is therefore entirely memory-bandwidth-bound: each token requires streaming the full KV cache out of HBM, so throughput is gated by bandwidth, not arithmetic. A single H100 can serve only ~1.9 users at full 128K context (vs ~20 at 8K).

This is why memory, not just compute, is the AI bottleneck — and why the constraint is being pushed up and down the hierarchy at once. Training stresses HBM bandwidth and capacity; inference with KV caching now also stresses NAND read speed, because the engineering responses to KV pressure all tier the cache across the hierarchy: Paged Attention (vLLM, 16-token pages evicted to CPU DRAM/NVMe), KV offloading (NVIDIA Dynamo, FlexGen, InstInfer), KV quantization (int8/int4), and GQA/MQA to shrink K/V heads. Empirically these work: Samsung's PM1753 SSD KV-offload test delivered 1.7x more concurrent users at equal latency, 1.5x more output tokens/sec under high concurrency, and 53% lower total power at only ~4% additional system cost (I/O pattern 92% reads, 96% of requests >1 MB — ideally suited to SSD sequential reads). FlexGen showed 100x higher throughput for OPT-175B; InstInfer ran attention inside the SSD to beat it 6.85x; NVIDIA Dynamo reports 14x faster time-to-first-token vs recomputing KV. The structural consequence is that KV-cache offloading has created a new enterprise-QLC-NAND demand tier (122-245TB QLC drives — Kioxia LC9 won FMS 2025 Best of Show; SanDisk BiCS8 "Stargate") that did not exist 18 months ago, plus a future High Bandwidth Flash (HBF) tier between HBM and NVMe (SanDisk + SK Hynix + Kioxia; 192 GB HBM → 3,120 GB HBF, ~16x density, first samples 2H 2026, applications 2027-2028). Note the bear counter-signal: server-side KV-cache compression (flagged by Morgan Stanley, Apr 2026) is a new factor that reduces DRAM intensity per workload — a headwind for DRAM-heavy holdings even as it lifts NAND.

Subsectors

The memory market is not one market — it is a stack of physically distinct technologies, each occupying a different point in the speed-cost-capacity space because no single physical mechanism can be simultaneously fast, dense, and cheap. A flip-flop made of six transistors reads in ~1ns but consumes huge area; a capacitor holding charge is dense but leaks; a floating gate is non-volatile but degrades with each write; a magnetic disk is cheap but mechanical. The result is a hierarchy spanning ~ten orders of magnitude in latency (0.3ns registers to 100s tape) and ~eight orders of magnitude in cost (millions of dollars per GB for SRAM to fractions of a penny for tape). What follows is each tier, the cell physics that defines it, the economics, and who profits.

DRAM (incl. DDR5)

Cell mechanism. In 1966, IBM's Robert Dennard invented the modern DRAM cell: one transistor plus one capacitor (1T1C). The capacitor holds charge to represent a 1 (or no charge for a 0). Cell area dropped to ~6F² (roughly 20x denser than SRAM's six-transistor cell). Three properties define DRAM and create permanent overhead: (1) Refresh — capacitors leak, so every ~64ms all rows must be read and rewritten, consuming ~5-7% of memory bandwidth; (2) Destructive read — reading a row depletes the capacitor, so the sense amplifier must immediately rewrite the data back; (3) Off-die latency — DRAM chips sit on DIMMs centimeters from the CPU. At 5GHz, light travels only ~6cm per clock cycle in vacuum (~4cm on copper), making the round trip physically too long to complete in one cycle. Round-trip latency is ~60-100ns, equivalent to 300-500 wasted CPU cycles per access. DRAM is volatile: lose power and everything vanishes.

Variants. DDR (server/desktop, latency-optimized); LPDDR (mobile, power-optimized, <2W idle); GDDR (graphics, throughput-optimized, 32-48 Gbps/pin on GDDR7, 192+ GB/s per device); HBM (AI accelerators — DRAM stacked vertically, covered separately below).

• DDR4 — 2014 vintage, server/PC, being phased out in datacenter but still volume in industrial/auto. Samsung and SK Hynix announced DDR4 lifecycle extensions on unexpected enterprise demand.
• DDR5 — current server/PC standard. DDR5 at 6400 MT/s, ~100 GB/s per DIMM. Datacenter standard is DDR5-4800 to DDR5-5600, with DDR5-6400 emerging on AMD's Turin platform. Per socket: 300-600 GB/s aggregate across 8-12 channels.
• LPDDR5/5X — mobile, low-power; recently entering datacenter for power-constrained AI inference. LPDDR5X at 6400 MT/s. iPhone 17 sources 60-70% of its LPDDR5X from Samsung.

DDR5 vs DDR4 step-up: 2x bandwidth (50→100 GB/s per DIMM), 17% lower voltage (1.2V→1.1V), dual 40-bit channels per DIMM (vs single 72-bit), burst length doubled (BL8→BL16), and on-die ECC standard. DDR5's registered DIMMs require registered clock drivers (RCDs) — a separate high-margin sub-market (Rambus, Montage, Renesas; see SRAM/hierarchy and HBM sections for the IP layer).

Economics and supply position. DRAM cost was ~$3-10/GB in 2025, volatile and driven sharply upward by AI demand. Meta reports DRAM is ~40% of rack cost; Microsoft estimates ~50% of server cost. DRAM contract prices rose +58-63% QoQ in Q1 2026; conventional DDR5/LPDDR5X prices rose 11 consecutive months as of Q1 2026; Samsung lifted Q2 2026 DRAM prices ~30% QoQ after an estimated ~100% surge in Q1 2026 (TrendForce). DDR4 8Gb pricing was flagged +60% in 2Q then decelerating into 2H (MS, Apr 19 2026). Three players control >95% of global DRAM (Samsung, SK Hynix, Micron), with 40-50% peak gross margins. Counterpoint DRAM revenue share 2024→2025: SK Hynix 33%→35% (surpassed Samsung as #1 for the first time, on Q4 2024 share of 36.6% vs 34.4% in Q3 2024); Samsung 41%→34% (−7pp, the visible cost of the HBM3E miss); Micron 21%→24%; CXMT 4%→5% (doubled, China structural threat building); Nanya ~1%. DRAM TAM ~$108B (2025) → ~$190B (2030) at ~12% CAGR. China's CXMT is 2-3 generations behind on process (16nm DDR5 vs Samsung 1a/1b/1c nm) but already disrupting domestic Chinese DDR4 procurement.

NAND Flash

Cell mechanism. A NAND cell is a single transistor with a "floating gate" of polysilicon trapped between two oxide layers. Programming forces electrons through the lower oxide via channel hot-electron injection (writing a bit takes ~20V — a violent act); electrons remain trapped with no power needed (non-volatile). Erasing pulls them back via Fowler-Nordheim tunneling. Reading senses whether the gate is charged. Cell area is ~4F². The act of programming and erasing degrades the tunnel oxide, so NAND is rated by program-erase (P/E) cycle endurance — and write is ~1,000x slower than DRAM, erase must happen in large blocks, and reads pull entire 4KB pages at a time (cells are wired in series like AND gates).

The cell taxonomy / endurance ladder — each additional bit per cell halves the voltage margin between states, trading endurance and retention for density:

Cell type	Bits/cell	Voltage states	P/E cycles	Retention	Use case
SLC	1	2	90,000-100,000	10+ years	Enterprise cache, niche industrial/military
MLC	2	4	3,000-10,000	5-10 years	Industrial, automotive — Macronix monopoly thesis lives here (sub-32GB eMMC)
TLC	3	8	1,000-3,000	1-3 years	Consumer SSDs, mobile (current sweet spot)
QLC	4	16	100-1,000	Weeks-months	Datacenter cold storage, hyperscaler bulk — Pink's enterprise-SSD thesis (Kioxia, SanDisk) lives here
PLC	5	32	<100 (research)	Days	Future archival tier; may never commercialize

QLC has 16 voltage levels with ~50mV margin between them, making it sensitive to noise, leakage, and wear-induced drift. Retention drops with temperature: every 10°C increase halves data-retention time.

3D NAND. Modern NAND stacks cells vertically using charge-trap flash (CTF), which traps electrons in discrete sites within a silicon nitride layer rather than a single floating gate — dramatically improving reliability at scale. More layers = more bits per wafer = lower cost/GB. Per-vendor 3D layer counts (2025-2026 production):

Vendor	Generation	Layers	Tech / notes
Samsung	V-NAND Gen 9 (V9)	286 (2×143 deck stacking)	TLC/QLC, 3.2 Gbps I/O, mass production 2024
Samsung	V-NAND Gen 10	400+ active	5.6 GT/s, WF-Bonding (wafer-to-wafer), TLC; unveiled ISSCC 2025, ramp 2025-26; Samsung licensed YMTC's hybrid-bonding patent for future 400L
SK Hynix	4D NAND	321	QLC, world's highest layer count in production (2025); >50% of bit output expected from 321L by end-2026
Micron	G9 NAND	276 (sources also cite 232L QLC G9)	TLC and QLC; first >200-layer QLC in commercial production (232L QLC mass production from April 2024, 2400 MT/s, 28% denser than competition at launch)
Kioxia	BiCS 8	218	CBA (CMOS directly Bonded to Array) wafer-bonding; main 2024-25 revenue driver
Kioxia	BiCS 10 (development)	332	+9% bit density vs BiCS8; 2026 shipments
YMTC	X4-9070	294 (150+144 bonded)	Xtacking (CBA-equivalent); X3 was 232L QLC at industry-record 19.8 Gbit/mm²; X5-9080 300+L planned

(Source A — sector primer — cites Samsung 286L V9, SK Hynix 321L, Micron 232L G9; the assignment frames these as Samsung 290L V9 / Micron 276L G9. Keeping both: the vault data is Samsung 286L V9, Micron 232L/276L G9, SK hynix 321L, with the 300L+ timeline confirmed by Samsung Gen 10 400L+ (ISSCC 2025), Kioxia BiCS 10 332L (2026), YMTC X5 300+L (late 2025), and SK Hynix's 321L already in production.)

CBA / Xtacking — Kioxia/SanDisk's CBA and YMTC's Xtacking both fabricate CMOS logic and the memory cell array on separate wafers and bond them with high-density vias, allowing each layer to be optimized independently and enabling higher density. YMTC was arguably first to commercialize.

Economics and supply. NAND ran $0.05-0.30/GB in 2025. NAND contract prices rose +70-75% QoQ in Q1 2026; some products saw 60%+ contract hikes (Nov 2025). Six players, fragmenting (Samsung, SK Hynix via Solidigm, Kioxia, SanDisk, Micron, YMTC), 30-50% peak GM. NAND TAM ~$65B (2025) → ~$115B (2030) at ~12%; enterprise SSD the fastest sub-segment ($25B→$55B, 17%). Counterpoint NAND revenue share 2024→2025: Samsung 33%→30% (−3pp, consistent with deliberate exit from low-margin eMMC/MLC); Kioxia 16%→16%; Micron 12%→13%; SanDisk 12%→12% (impressive post-WDC-spin); SK Hynix 11%→11%; YMTC 7%→10% (+3pp — the single most concerning data point in the complex for the durability thesis: gaining share despite the 2022 US Entity List); Solidigm 9%→8%. Crucially, the entire NAND supply chain is sold out through CY2026 (Kioxia, SanDisk, Samsung, SK Hynix all confirm), with sell-side modeling shortage through 2028. SanDisk projects 2026 bit demand growth 20-22% vs bit supply growth 15-17%. Micron is the only major maker deliberately cutting NAND wafer starts (>10% structural cut in FY2025) for pricing discipline. Industry NAND capex is +5% in 2026 ($21.1B→$22.2B), focused on process upgrades and hybrid bonding, not greenfield wafers — which is why no meaningful new supply arrives before late 2027-2028.

NOR Flash

NAND cells are wired in series (like AND gates), so reads must pull entire 4KB pages. NOR cells are wired in parallel (like OR gates), giving every byte its own access path. This makes NOR slow to write but fast to read at random addresses, and — critically — it supports execute-in-place (XIP): the CPU fetches and runs instructions directly from flash without copying to RAM first. Microcontrollers in cars, IoT devices, BMC controllers in servers, and industrial systems rely on XIP. NAND cannot do this because page reads are too slow and require ECC handling. NOR holds firmware that runs in-place; NAND holds files that get loaded into RAM first — different chips, different markets, different competitive dynamics.

The exits. Most makers left NOR because margins were low and scaling became uneconomic below 65nm: Micron exited ~2017 (sold to Numonyx/JV partner; the Intel-STMicro NOR JV Numonyx had been sold to Micron in 2010); Spansion (the AMD/Fujitsu NOR JV) merged into Cypress in 2015, which Infineon acquired in 2020 (Infineon retained automotive-focused NOR but with less scale than the Cypress peak); Samsung exited ~2010-2013. The supply base contracted from ~8 credible suppliers in 2010 to ~4 today.

Survivors and structure. Total NOR market ~$4-5B (2024; sources vary $3.0-5.5B by serial/parallel scope), growing to ~$10.7B by 2034 at ~8.2% CAGR. ~4-player oligopoly post-consolidation, 30-45% GM:

• Winbond (2344.TW) — global #1 by serial NOR shipments since 2020, ~20-22% share; W25Q (ubiquitous SPI NOR), OctalNAND, QspiNAND.
• Infineon (incl. Cypress, IFX.DE) — ~18-20%, automotive NOR (HYPERBUS, ASIL-grade).
• Macronix (2337.TW) — ~16.1% (Omdia 2024); serial + parallel NOR; OctaFlash; ASIL-D / ISO 26262 automotive focus.
• GigaDevice (603986.SS, China) — ~12-15%, growing fast in China, state-backed.
• Long tail: ISSI (private, ~5-7%), Renesas/IDT (~4-5%), Microchip/SST (~3-5%).

Macronix, Infineon, Winbond and GigaDevice together hold ~60-65% of global automotive NOR revenue. Automotive ASIL-D qualification (IATF 16949, ISO 26262) creates multi-year switching costs and incumbent protection; billions of MCU/MPU designs are locked onto NOR for code storage and cannot quickly switch suppliers. Key partnership: Macronix OctaFlash supplies memory for STMicro's STM32N6 AI-accelerated MCU platform (announced early 2025).

The sub-32GB MLC eMMC monopoly thesis — "the single best-defined stock idea from this research" (Macronix, 2337.TW). Although strictly an eMMC/MLC-NAND story, the thesis sits structurally adjacent to NOR because it rests on the same dynamic (commodity giants abandoning a low-margin specialty niche to the survivors). The Big Four NAND makers are end-of-life-ing their sub-32GB MLC eMMC product lines to free capacity for HBM and high-density NAND: Samsung (Oct 2025), Micron (2024), Kioxia (2027 LTS), SK Hynix (2027). The end markets that need it — TVs, set-top boxes, smartwatches, automotive telematics, drones, server BMC chips — cannot easily switch to TLC (controller redesigns, firmware changes, and 8+ year automotive supply-continuity requirements create structural lock-in). As the Big Four exit, Macronix becomes the only credible global sub-32GB eMMC supplier post-2028.

Macronix is converting from 2D MLC (legacy, high cost/bit) to 3D TLC NAND (3-9x more bits per wafer): cost drops while ASPs surge as supply exits. KGI's March 2026 initiation (Outperform, NT$300 PT vs ~NT$132): eMMC revenue NT$0.86bn (2025) → NT$56.4B (2026) → NT$230B (2027) — a 265x expansion in two years, eMMC rising from ~3% to ~75% of revenue, with gross margin jumping from ~18% (FY2025) to ~68% (FY2026F) to ~82% (FY2027F), and EPS NT$30.04 (FY26) / NT$107.25 (FY27). KGI's bull math = three multipliers: wafer starts ×17 (FY25 ~1k wpm → 4Q26 8k → 3Q27 17k, gated by 18-month ASML Immersion DUV lead time); bit output per wafer ×2.5-7 (19nm MLC 28,416 Gb/wafer → 3D TLC 48L 129,920 Gb (4.6x) → 96L 200,192 Gb (7.0x)); ASP/Gb ×7.5 (FY25 US$0.07 → FY26 US$0.42 (+505%) → FY27 US$0.53). Combined ×35 bit output × ×7.5 ASP = ×262 revenue. Confirmation is already visible: Q1 2026 contract prices for sub-32GB eMMC are up 100-200% QoQ (8GB +183%, 4GB +165%, 16GB +147%).

Important nuance (STF Q1 2026 call, Apr 27 2026): Dr. Wu told investors "please forget about AI. eMMC has essentially nothing to do with AI directly" — the surge is supply-side (Big Four exited a $1-2B niche too small to bother with), not demand-side. This matters for durability: if supply-driven, prices revert when supply rationalizes (Winbond re-entry takes 24-36 months from decision to volume = a 2028-2029 window). Source disagreement on the EPS magnitude is wide: KGI/STF FY26 EPS NT$30.04 / FY27 NT$107.25; Morgan Stanley (OW) only NT$5.90 / NT$19.61, PT NT$202; sell-side consensus NT$4.59 / NT$8.03, PT NT$176. MS sits at ~1/5 of KGI, implicitly assuming slower wafer-in ramp, lower 96L yield (KGI assumes 68-70% by mid-2026; NAND OEMs typically need 4-8 quarters to go 50%→70%), or ASP not holding through FY27. STF's four risks: 3D TLC 96L yield (no independent visibility into Macronix yields); ASML equipment delivery timing; Chinese substitution (TVs+STBs are ~52% of low-cap eMMC TAM by volume, exposed to GigaDevice+YMTC); Winbond re-entry capping elevated margins 2028-2029. The thesis is an option, not a fact, until Q1-Q2 2026 actuals confirm KGI's price/volume assumptions — entry discipline is to wait <NT$110 or for a clean post-earnings beat (first test ~early Aug 2026), max 2-3% position at first entry.

HBM (High Bandwidth Memory)

Yes, HBM is DRAM. The cells are 1T1C, identical to DDR5. What differs is the packaging: (1) multiple DRAM dies (8, 12, or 16) are stacked vertically; (2) Through-Silicon Vias (TSVs) etched through each die provide vertical signal paths; (3) microbumps connect adjacent dies; (4) the stack sits on a silicon interposer next to the GPU/ASIC die, packaged via CoWoS (Chip-on-Wafer-on-Substrate, TSMC's process — TSMC holds ~85% of HBM CoWoS, 55-65% GM). The result is a wide parallel bus (1024 bits per stack) at modest clock speeds, delivering enormous bandwidth at low power.

Generation	Speed	BW/stack	Capacity	First production	Reference GPU
HBM	1 Gbps	100 GB/s	4-8 GB	2015	AMD Fiji
HBM2	2.4 Gbps	240 GB/s	8-16 GB	2016	NVIDIA P100
HBM2e	2.4 Gbps	280 GB/s	16-32 GB	2018	NVIDIA V100
HBM3	6.4 Gbps	819 GB/s	24-36 GB	2022	NVIDIA H100
HBM3e	8-9.6 Gbps	1.0-1.2 TB/s	36-48 GB	2023+	H200, B200
HBM4	8-11.7 Gbps	2.0 TB/s	4-64 GB	2025-26	Vera Rubin

NVIDIA H100: 80 GB HBM3 across 6 stacks, 3.35 TB/s aggregate. NVIDIA B200: 192 GB HBM3e across 8 stacks, 8.0 TB/s. Progression runs 8-Hi → 12-Hi stacks (HBM3E 8Hi = 24GB, 12Hi = 36GB) toward HBM4 (Micron's HBM4 36GB 12-high shipping to Vera Rubin from Q1 CY2026; 48GB 16-high sampled; Samsung HBM4 at 11.7 Gbps).

Bit-share economics — why HBM is the whole game. HBM consumes only ~5-8% of DRAM bits but commands ~20-30%+ of DRAM revenue/profit. HBM3E prices roughly 5x per-GB over commodity DDR5 — the primer cites $25-50/GB for HBM3E vs $3-8/GB for DDR5 (premium ~3-5x to ~5x+); per-stack ASP runs ~$300-500. On a GPU, HBM content is ~$25,000-30,000 per GPU (e.g. a GB200 NVL72 rack = 72 GPUs × 192GB = 13.8TB of HBM3E), consuming ~20-25% of total GPU cost and rising with HBM4. HBM is decoupled from the commodity cycle: sold under multi-year contracts to NVIDIA/AMD/hyperscalers, capacity sold out 18+ months forward, sticky pricing, 60%+ margins — closer to the TSMC model than to historical Samsung Memory. HBM TAM ~$30B (2025) → ~$130B+ (2030) at ~34% — growing ~3x the broader memory market, so that by 2030 HBM alone (~$130B) roughly equals the entire 2025 DRAM market (~$108B).

TSV + stacking yield-compounding constrains supply. Stacking is done with TSVs and requires wafer-bonding capacity that takes 18-24 months to build; yields compound multiplicatively across each die in the stack, so 12-Hi and 16-Hi are progressively harder to yield than 8-Hi. There is effectively no spot market — every wafer is spoken for, SK Hynix's 2025 capacity was pre-committed before end-2024, and HBM4 demand is described by SK Hynix as "exceeding capacity for the next 3 years." HBM wafer-level burn-in is mandatory with no substitute (AEHR's FOX-XP/WaferPak is the direct beneficiary). SemiConSam frames the endpoint: HBM is becoming foundry-like with custom HBM (cHBM) — base-die customization, foundry-node integration, customer-specific specs — "from that point on, HBM from DRAM manufacturers starts to resemble a foundry business."

The three players and Samsung's stumble. SK Hynix originated the commercial HBM-for-AI ecosystem via NVIDIA and dominates at ~62% share (Q2 2025); HBM was 30% of its DRAM revenue in Q3 2024, >40% by Q4 2024; FY2025 op margin 49% (all-time record), 72% in Q1 2026 — pricing power driven by HBM3E to NVIDIA Blackwell, not a commodity up-cycle. Micron ~21-24%, the fastest share gainer, with HBM run-rate ~$8B annualized exiting FY2025 (HBM3E 8Hi in NVIDIA GB200, 12Hi in GB300 and AMD MI355X; a fourth large HBM customer; entire CY2026 incl. HBM4 sold out). Samsung's HBM3E Nvidia-qualification stumble is the defining story of 2024-2025: its HBM3E had thermal-stability problems and failed NVIDIA qualification repeatedly through 2024, so share collapsed from ~41% (Q2 2024) to ~17% (Q2 2025) — a −7pp DRAM-revenue hit overall — while it kept shipping older HBM3 as SK Hynix shipped HBM3E 12Hi 36GB (first to mass-produce, Sep 2024). Samsung finally cleared NVIDIA's 12-layer HBM3E qualification in September 2025, recovered to ~35% (Q3 2025) on catch-up shipments, and is targeting >30% of NVIDIA's HBM4 supply for 2026 (samples delivered Dec 2025) — but the credibility gap remains. The Q2 2025 qualification failure cost Samsung an estimated ~$8-10B in lost H1 2025 HBM revenue. China (CXMT) is exploring HBM-equivalent products via TSV but is 2-3 generations behind, a 2027-2028+ overhang at earliest.

SRAM / Memory Hierarchy

Cell mechanism. The 6T SRAM cell stores a bit using two cross-coupled inverters that lock the bit in a stable state, plus two access transistors gating reads/writes — no refresh, no destructive read, no wear. Read latency is ~1ns because the signal is strong, wires are short (millimeters on a die), and reading does not disturb the stored value. The catch is six transistors per bit: at 3nm a single SRAM cell occupies ~0.04 μm² (~120F²), so multi-GB arrays would consume gigawatts of standby leakage. SRAM is therefore reserved for CPU L1/L2/L3 caches and on-die GPU memory. NVIDIA H100 has 50 MB L2 cache and 228 MB shared memory (SRAM) across 132 streaming multiprocessors; AMD's 3D V-Cache stacks additional SRAM via TSVs to reach 1.15 GB on Genoa-X variants. SRAM delivers 20+ TB/s on-chip bandwidth; FlashAttention exploits this tier by tiling attention to maximize SRAM reuse — but SRAM is fundamentally too small to hold weights or KV caches (Groq's LPU tried 230 MB SRAM as primary memory; Cerebras likewise — both had to retrofit external DRAM once "LLMs overwhelmed on-chip SRAM capacity").

The full hierarchy (NVIDIA's view). Each tier exists because removing it would create an unacceptable gap in speed-cost-capacity, and the system works only because of locality of reference — temporal (recently accessed data reused soon) and spatial (nearby addresses accessed next) — which lets a cache holding just 1-5% of data serve 80-95% of accesses. Without it, an all-SRAM 512GB server would cost ~$2.5M vs ~$1,500 in DRAM (a ~1,700x difference).

Tier	Latency	Bandwidth	Capacity	Cost/GB	Volatile?
CPU registers	~0.3 ns	200+ GB/s	128 B-4 KB/core	embedded (~$M/GB)	Yes
L1 cache (SRAM)	~1 ns	50+ GB/s/core	32-128 KB/core	~$12,500 (die area)	Yes
L2 cache (SRAM)	~4 ns	10-20 GB/s/core	1-2 MB/core	~$12,500	Yes
L3 cache (SRAM)	~10-20 ns	400-900 GB/s/socket	256 MB-1.15 GB	embedded	Yes
GPU shared SRAM	<5 ns	5+ TB/s/SM	228 MB (H100)	embedded	Yes
HBM3e (on GPU)	~10-30 ns	8 TB/s (B200)	192 GB	$25-50	Yes
DDR5 DRAM	~80 ns	100 GB/s/DIMM (300-600/socket)	16-256 GB	$3-8	Yes
CXL memory	~150-500 ns	20-64 GB/s	64 GB-2 TB	$1-5	Mostly
NVMe SSD	~10-20 μs	7-14 GB/s	960 GB-122 TB	$0.07-0.30	No
SATA SSD	~100 μs	560 MB/s	256 GB-30 TB	$0.05-0.10	No
HDD	~8-12 ms	200-270 MB/s	1-36 TB	$0.01-0.02	No
LTO tape	~45-100 s	400 MB/s	18-40 TB	$0.004-0.007	No

L1 hit rates run 85-95%; the combined cache hierarchy filters 95-99% of accesses before they reach DRAM. AMAT = Hit Time + (Miss Rate × Miss Penalty): a 95% L1 hit rate with a 100ns miss penalty yields ~6ns effective average — near-SRAM speed at DRAM-scale capacity. SRAM has no major pure-play investable name in the memory complex (it is embedded in CPU/GPU dies); the closest specialty SRAM exposure is ISSI (private since 2015, ~$775M Chinese-consortium buyout; high-speed synchronous SRAM and PSRAM, automotive ~40-45% of revenue).

CXL / Compute Express Link

The 800x latency chasm CXL fills. Between DRAM at ~100ns and NVMe SSDs at ~80,000ns lies an ~800x latency gap — the memory hierarchy's most painful discontinuity. Intel's Optane Persistent Memory once bridged part of it at ~300ns, but Intel discontinued the entire Optane line in 2023. The successor is CXL (Compute Express Link), an open standard built on the PCIe physical layer that adds cache-coherent memory semantics. CXL Type-3 memory expanders — currently DRAM-based modules from Samsung, Micron, and Astera Labs — attach via PCIe 5.0 at ~150-500ns latency (roughly 2-5x slower than local DRAM but 100-500x faster than flash), with 512 GB to 2 TB per module at ~$1-5/GB.

Deployment and the TAM-expander thesis. Microsoft Azure deployed the industry's first commercial CXL memory in its M-series VMs in 2025 (Astera Labs controllers), increasing memory capacity by 50%; the CXL market exceeded $1 billion in 2025. Linux kernel 5.15+ supports CXL devices as CPU-less NUMA nodes, automatically demoting cold pages from local DRAM to CXL and promoting hot pages back via multi-generation LRU — transparent to applications.

Why CXL is a DRAM-TAM expander, not a substitute. The deeper promise is memory pooling / disaggregation — multiple servers sharing a common memory pool via switches. Google reports average DRAM utilization of only ~40%; Microsoft measures 25-30% of server DRAM as "stranded" (provisioned for peak, idle most of the time). Even first-gen CXL disaggregation achieves a 9-10% reduction in total DRAM (hundreds of millions in hyperscaler savings); Alibaba's PolarDB CXL disaggregated buffer pool shows 2.1x throughput vs RDMA. CXL 3.0 switching extends this to multi-rack pooling at 100+ TB scale with multi-level switching fabrics and standardized CXL Fabric Managers (expected 2026-2027), turning more of the addressable server-memory footprint into sellable DRAM modules attached over PCIe — expanding DRAM TAM rather than cannibalizing it. (Caveat: MS flags KV-cache compression as a new bear factor that could reduce DRAM intensity per workload, a headwind across DRAM-heavy holdings.)

HBF (High Bandwidth Flash)

HBF is an emerging NAND-based memory tier sitting between HBM and NVMe SSD storage — applying HBM-style vertical stacking and wide interfaces to NAND rather than DRAM, to deliver HBM-comparable bandwidth at 8-16x the capacity. SanDisk + SK Hynix + Kioxia are co-developing it (per Vik's Newsletter, "High Bandwidth Flash: NAND's Bid for AI Memory," Sep 22 2025). SanDisk's demo: 192GB HBM → 3,120GB HBF (16x density). First samples 2H 2026; useful applications "only become evident in 2027-2028."

What HBF can and cannot do. It cannot replace HBM: microsecond latency vs HBM's nanoseconds, ~78 pJ/bit power vs HBM's 2-3 pJ/bit, and NAND endurance limits. Best fit per Vik: GDDR replacement in prefill compute chips (e.g. NVIDIA Rubin CPX) where bandwidth tolerance is wider; for models like Kimi 2 (1T params, ~1TB memory), HBF capacity removes the need for pipeline parallelism. For Pink's positions (SNDK + 285A.T, both co-development partners), HBF is real durability optionality post-2027 — best treated as a free option on top of the eMMC/NAND durability thesis, not a near-term catalyst (sizing impact materializes 2027-2028).

KV-Cache / Inference-Memory Tier

Why it exists. In transformer attention, each new token must attend to all previous tokens; without caching, every token requires recomputing keys (K) and values (V) for the entire context (quadratic in sequence length). KV caching stores K and V from prefill so decode becomes ~linear — at a steep memory cost. KV size = 2 × layers × heads × head_dim × seq_len × bytes_per_value. For Llama 3 70B at 128K context in FP16, ~40-42 GB per user session — more than an entire A100, and more than half an H100's 80GB HBM. A single H100 serves ~1.9 users at full context (or ~20 at 8K). With model weights (140 GB FP16 for Llama 3 70B) plus activations plus per-user KV cache all contending for HBM, the three-way pressure drives offloading down the hierarchy. The decode phase is entirely memory-bandwidth-bound; NVIDIA GPU FLOPs grew 80x from 2012-2022 while HBM bandwidth grew only 17x — the "memory wall."

The new structural NAND demand tier. Engineering responses: Paged Attention (vLLM, 16-token pages evicted to CPU DRAM/NVMe); KV offloading (NVIDIA Dynamo, FlexGen, InstInfer — tiering KV across HBM/DRAM/NVMe); KV quantization (int8/int4, 2-4x reduction); GQA/MQA (Llama 3 uses GQA). Research/production proof points: FlexGen (ICML 2023) achieved 100x throughput on OPT-175B by offloading across GPU/CPU/SSD; InstInfer (2024) performed attention inside the SSD (exploiting 11.2 GB/s internal flash-channel bandwidth) to beat FlexGen 6.85x; NVIDIA Dynamo (2025) reports 14x faster time-to-first-token vs recomputing KV. Samsung's PM1753 test (2025, 8× H100 NVL): SSD-based KV offload gave 1.7x more concurrent users at equal latency, 1.5x more output tokens/sec under high concurrency, 53% lower total power — at only ~4% additional system cost (I/O pattern 92% reads/8% writes, 96% of requests >1MB, ideal for SSD sequential strengths). The economics flip per scenario: for single-user latency-sensitive decode, FlexGen shows KV access escalating to 98.94% of decode latency when on SSD — so offload only makes sense for throughput/batch and high-concurrency. This is why SanDisk's BiCS8 QLC "Stargate" drive and Kioxia's LC9 (245.76TB QLC, FMS 2025 Best of Show) are qualifying at hyperscalers specifically for KV-cache offload, why Samsung calls out "Key Value SSD for AI inference," and why data center is set to overtake mobile as the largest NAND market in 2026 — for the first time in ~15 years. SemiAnalysis frames HBM as the primary winner; the second-order winner is enterprise QLC NAND, where Kioxia, SanDisk, Micron and Samsung compete.

The durability debate (NBM/LTA evidence). Whether this new inference-memory demand is structural or cyclical is the single most important investment question in memory. The empirical anchor is SanDisk's NBM ("New Business Model") disclosure at Q3 FY26 (Apr 30 2026): 5 NBM agreements signed (3 in Q3, 2 in Q4), ~$42B minimum contractual revenue from the 3 Q3 contracts, >$11B aggregate financial guarantees across all 5, $400M of prepayments on the balance sheet, >1/3 of FY27 bits locked, max 5-year duration, fixed near-term / variable longer-term pricing, with walkaway treatment that retains the prepayment and seizes guarantees (escrow portion recognized at 100% gross margin). The print itself was extraordinary — revenue $5.95B (+251% YoY), 78.4% non-GAAP GM, 70.9% op margin, $23.41 EPS, $2.96B FCF (49.7% margin), net cash, $6B buyback — yet SNDK fell on the news, on three bear interpretations: fixed pricing on 1/3 of FY27 bits caps upside if spot keeps rising; bit shipments were flat YoY / down high-teens QoQ (top-line is ASP-driven); and the $42B "minimum" has an opaque GAAP recognition path. The phenomenon is industry-wide: SK Hynix (all 2026 sold out under binding contracts, prepayments 10-30% of contract value vs <5% historically, Microsoft/Google named), Samsung ("Securing Profit Stability Under Favorable Terms"), and Micron (entire 2026 HBM incl. HBM4 committed, customer prepayments common) have all disclosed LTAs with prepayments — but Kioxia (285A.T) had no equivalent customer-side NBM disclosure as of May 2026 (a meaningful information gap; it receives $1.165B in installments from SanDisk 2026-2029 for the Yokkaichi JV extension, but that is supplier-side, not customer demand). The bull case: customers locking in years of supply at fixed-price floors with non-refundable prepayments signal that they themselves view memory shortage as a multi-year structural problem — implying NAND/HBM should re-rate off cyclical multiples toward contracted-infrastructure visibility. SemiConSam's structural anchor reinforces this ("the chicken-game era is over" after three consolidation rounds left only Big 3 in DRAM; "shouldn't we stop valuing memory companies by P/B now?"). The bear case: memory has always reverted to the mean, YMTC's +3pp NAND share gain shows Chinese capacity destabilizing pricing despite the Entity List, and current 70-80% gross margins are unsustainable.

The application-layer KV-reuse economics. The same KV-caching that drives the hardware tier also drives an application-layer cost economy. Anthropic's prompt caching (public beta Aug 14 2024, GA Dec 17 2024) stores precomputed KV states for prompt prefixes; a subsequent request sharing an identical prefix skips attention recompute for those tokens — up to 90% cost reduction and 85% latency reduction on long prompts. Implementation requires explicit cache_control: {"type": "ephemeral"} breakpoints (max 4 per request; prefix order tools → system → messages), with a default 5-minute TTL (refreshed on each hit; 1-hour option at higher cost; Claude Code users reported the TTL may have been silently cut to ~3 min in Dec 2025). Minimum cacheable content: 1,024 tokens (Sonnet/Opus), 2,048 (Haiku). Pricing has three tiers: standard input at base; cache writes at 1.25x base (5-min TTL) or 2x base (1-hr TTL); cache reads at 0.1x base (90% discount) — so the write surcharge means a developer must achieve ≥2 subsequent cache hits per write to break even (for Sonnet 4.5: $3/MTok base, $3.75 cache write, $0.30 cache read). The cost math favors high-reuse: $0.75 vs $1.45 for a 100K-token context repeated 10x. Versus competitors, Anthropic is the only major provider requiring explicit API modification (OpenAI Oct 2024 fully automatic, no write surcharge, 50% read discount; Gemini implicit up to 75-90% plus explicit with $1/MTok/hr storage; DeepSeek automatic 90%), trading ease-of-adoption for 100% cache-hit reliability (vs OpenAI's ~50% probabilistic hit rate) and the deepest discount — optimized for power users. Note: prompt caching is an application-level feature running on whatever compute Anthropic already uses (Google TPUs, AWS Trainium, NVIDIA GPUs); there is no separate "caching payment" to Google — Anthropic's cloud spend is subsumed in general compute deals (~$42B GCP TPU RPO + ~$10B Broadcom hardware; $8B Amazon / Project Rainier Trainium 2; $5B + $30B Azure / 1GW NVIDIA).

Value chain

The memory value chain runs upstream-to-downstream in four stages, and the AI/HBM transition is actively redistributing where profit pools sit within it. The canonical map (memory-sector-primer Section 7):

[Memory IP & EDA] → [Wafer fab equipment] → [Foundries / IDMs] → [Packaging / Test] → [SSD/Module assembly] → [System integrators] → [End customer]
 Rambus, Synopsys,    ASML, Applied,         Samsung, SK Hynix,   TSMC CoWoS, Amkor,    Sandisk, Kingston,      Dell, HPE, Foxconn,     Hyperscalers,
 Cadence, Montage     Lam, KLA, TEL          Micron, Kioxia,       ASE, Nepes; probe     ADATA, Crucial          NVIDIA, AMD, Intel      OEMs, enterprises
 (RCD)                                        Macronix, Winbond     (JEM, Micronics)

The stages and their profit pools

Layer	Sample players	Gross margin	Concentration
Memory IP & DDR5 RCD chips	Montage (688008.SS), Rambus (RMBS), Renesas	60–75%	3 players in DDR5 RCD
Wafer fab equipment	ASML, Applied Materials, Lam, KLA, Tokyo Electron	45–55%	~5 players for advanced memory tools
Memory IDMs (DRAM)	Samsung, SK Hynix, Micron	40–50% peak	3 players control >95% DRAM
Memory IDMs (NAND)	Samsung, SK Hynix/Solidigm, Kioxia, Sandisk, Micron, YMTC	30–50% peak	6 players, fragmenting
HBM packaging (CoWoS)	TSMC dominant, Samsung distant 2nd	55–65% (TSMC)	TSMC ~85% of HBM CoWoS
Specialty memory (NOR, low-density DRAM)	Winbond, Macronix, Infineon, GigaDevice	30–45%	~4 NOR players post-consolidation
Probe card (memory/HBM test consumable)	JEM (6855/6855	6855), Micronics (6871), FormFactor, Technoprobe, MPI	40–50%
Module assembly	Kingston (private), Crucial (Micron), ADATA, Patriot	5–15%	Fragmented

Upstream equipment earns through the cycle on capex (revenue is capex-driven, felt on a lag when IDMs cut). Memory IDMs capture most of the value in commodity DRAM/NAND, but violently cyclically — margins swing from +50% operating at the top to deeply negative at the trough (all three DRAM makers lost money on an operating basis in the 2023 trough; Samsung DS lost ~KRW 14.9tn). The biggest value capture in the AI cycle has been at the IDM layer (HBM premium) and at the TSMC CoWoS packaging layer (scarcity). The IP/RCD layers (Montage, Rambus) earn high margins on small revenue — high-quality compounding exposure.

How HBM shifts value to advanced packaging and the logic base die

HBM is the single most important development in memory economics in a decade, and it changes the value distribution, not just the size of the pie:

• HBM is just DRAM, repackaged. The cells are 1T1C identical to DDR5; what differs is the packaging — 8/12/16 DRAM dies stacked vertically, TSVs (through-silicon vias) etched through each die for vertical signal paths, microbumps between dies, the stack sitting on a silicon interposer alongside the GPU/ASIC die, packaged via TSMC's CoWoS (Chip-on-Wafer-on-Substrate). Result: a 1024-bit-wide parallel bus at modest clock, delivering huge bandwidth at low power.
• HBM sells at 5–7x the price per bit of commodity DRAM (~$25–50/GB for HBM3e vs ~$3–8/GB for DDR5), at 60%+ margins. SK Hynix's FY2025 49% operating margin — an all-time record for any memory maker — was driven by HBM3E to NVIDIA Blackwell, not a commodity up-cycle. This is closer to the TSMC business model than the historical Samsung Memory model.
• HBM is a capacity sink: it consumes ~2–3x the wafer area per bit (3× silicon vs standard DDR5 per Micron), tying up fab capacity and tightening commodity DRAM supply — a second-order benefit to the IDMs' commodity book.
• The logic base die is becoming a custom logic chip. With "custom HBM" (cHBM), the bottom layer of an HBM stack shifts from a passive memory die to a custom logic base die made by a foundry — TSMC for SK Hynix, including HBM4. SemiConSam's framing: "From that point on, HBM from DRAM manufacturers starts to resemble a foundry business." This pulls value out of the memory maker and into the foundry, and gives buyers (NVIDIA) a hook to customize.
• Stacking, TSV, and KGD (Known-Good-Die) yield are now competitive moats. This is differentiation the old commodity model never had — it separated the HBM winner (SK Hynix, first to mass-produce 12Hi 36GB HBM3E Sept 2024, ~62% share) from the laggard (Samsung, which failed NVIDIA's HBM3E 12-layer qualification repeatedly through 2024, share collapsing ~41% → ~17%, only clearing qual September 2025).
• HBM test intensity is a new bottleneck. Each die in a stack must test as KGD before stacking — a bad die discards the whole stack. KGD = more probe touchdowns per die and per stack, raising probe-card consumption structurally. The probe-card layer (below) is the AI-test pick-and-shovel beneficiary; HBM burn-in (Aehr WaferPak) is a parallel mandatory test consumable.

Pick-and-shovel / bottleneck-layer plays

The most attractive structural positions in memory are often not the IDMs but the indispensable bottleneck components that attach to every module or every die and sidestep the raw commodity cycle.

The DDR5 RCD oligopoly — the canonical bottleneck. Every DDR5 RDIMM (server-grade Registered DIMM) needs a Registered Clock Driver (RCD) — a chip that buffers command/address signals between the memory controller and the DRAM chips, improving signal integrity and allowing more chips per channel. LRDIMMs add data buffers on top; the next-gen server DIMM (MRDIMM) needs even more sophisticated buffering. The RCD attaches to every server RDIMM, so it scales directly with DDR5 server-memory content — an AI/server memory play that sidesteps the commodity DRAM cycle. The market is a tight three-firm oligopoly at 60–75% gross margin:

Vendor	Share	Notes
Montage Technology (688008.SS)	~36.8%	China-based, leading share; also sells MXC and companion chips
Renesas (ex-IDT)	~30%	Japan; acquired IDT's memory-interface business
Rambus (RMBS)	~25%	US, IP-rich; licenses memory interface IP + sells RCD/buffer chips for DDR5/LPDDR5. Vault page is a stub (run /deep-dive RMBS). Every server DIMM using registered memory needs a Rambus RCD.

Around the RCD sit data buffers, temperature sensors, PMICs, and SPD hubs on the DIMM — Montage and Renesas both sell these companion chips, expanding dollar content per module.

The probe-card consumable layer — a second bottleneck. Every die that ships is physically touched by a probe card (the consumable interface between ATE — Advantest/Teradyne — and the wafer), and each card has a finite touchdown life, so demand scales with wafer volume × chip complexity × node transitions. Five players hold ~80% of advanced probe-card revenue: FormFactor (FORM, US, broadest portfolio), Technoprobe (TPRO.MI, Italy, #1 at TSMC advanced node), JEM/Japan Electronic Materials (6855.T, Pink holds, #1 Japan, HBM-leveraged), Micronics Japan (6871, #2 Japan, memory + logic vertical/MEMS), and MPI Corp (6223.TW). HBM is the swing variable: KGD test on stacked dies raises probe-card consumption per AI chip 2–3x vs prior-gen logic. (Note: 6871/Micronics is a test-consumable maker, NOT a memory maker — it sits at the packaging/test layer of the chain.)

CXL as an emerging adjacent layer. Compute Express Link (cache-coherent interconnect over the PCIe physical layer) attaches pooled, expandable DRAM beyond the limited DIMM slots near a CPU, at ~150–500 ns latency (vs ~80 ns local DRAM, but 100–500× faster than flash). It fills the ~800× DRAM-to-NVMe latency chasm left when Intel discontinued Optane in 2023. CXL Type-3 expanders come from Samsung, Micron, and Astera Labs (controllers). Microsoft Azure deployed the first commercial CXL in its M-series VMs in 2025 (+50% memory capacity, Astera controllers); the CXL market exceeded $1B in 2025. CXL 3.0/4.0 extend to multi-rack memory pooling — even first-gen disaggregation cuts total DRAM ~9–10%.

Industry structure and geopolitics

Memory is the closest thing semiconductors have to a pure commodity — DRAM and NAND from different makers are largely interchangeable at the chip level, buyers qualify multiple suppliers and switch on price, producing violent 3–4-year boom-bust cycles. SemiConSam argues the "chicken-game" era is structurally over after three rounds of consolidation (2007 Taiwan crisis → Qimonda bankruptcy 2009; 2010 Elpida volume gambit → Elpida bankruptcy 2012; Micron rolling acquisitions), leaving only the Big 3 in DRAM. Further consolidation is blocked: Korea won't let Samsung kill SK Hynix; the US won't let Samsung kill Micron; antitrust watches. That commodity structure makes the industry a geopolitical battleground, and policy has reshaped the supplier set:

• US Entity List — YMTC (December 2022). China's NAND champion YMTC was added to the US Entity List in December 2022, cutting off direct purchase of US-origin tools and IP. YMTC responded by partnering with Chinese domestic equipment makers (AMEC etch, Naura, Piotech, SMEE) and crossing the >50% domestic-equipment threshold at its Phase 3 Wuhan fab. It continues to advance (X4-9070 294-layer via Xtacking wafer bonding; X5-9080 300+ layers planned) and add capacity — a recurring bear-case supply risk.
• DoD military designation (February 2024). YMTC was added to the US DoD list of Chinese military companies in February 2024 — a second, separate designation compounding the investment/procurement chill.
• CHIPS Act (~$39B). US CHIPS Act provides ~$39B in direct grants; primary memory-relevant recipients Micron ($6.1B), Samsung ($6.4B, Texas fab partially funded), TSMC ($6.6B). Anchors domestic onshoring; Micron is the only US-based memory maker (Idaho + Taiwan).
• Other industrial policy. Japan: Kioxia received METI subsidies ($2B+) for its Kitakami fab; Japan Investment Corp is a potential strategic backstop. China: Big Fund III ($47B) backs CXMT (DRAM) and YMTC (NAND). Taiwan: Macronix, Winbond, Powerchip operate under the US-aligned export regime; Macronix's Lujhu Phase 2 fab is approved.
• The China wildcard. China-domestic memory (CXMT in DRAM, ~5% global share and doubling from 2024; YMTC in NAND, ~10% and rising despite sanctions) substitutes for low-end DDR4/DDR3 and 2D NAND but cannot yet do HBM (3+ generations behind), advanced DDR5 (1–2 behind), or sub-32GB MLC eMMC (no credible substitute). This caps China's near-term threat but its commodity-capacity additions are the single biggest risk to the supply discipline the cycle's profitability hinges on.

The HDD recording roadmap and the SSD/HDD boundary

NAND competes against hard disk drives at the cold-storage tier, and the HDD recording roadmap sets where that boundary sits:

• PMR (Perpendicular Magnetic Recording) — mainstream for ~15 years, plateaued at ~1 Tb/in².
• SMR (Shingled Magnetic Recording) — overlaps tracks like roof shingles for ~25% density gain at the cost of slower random writes (read-modify-write); archival/read-heavy capacity drives.
• HAMR (Heat-Assisted Magnetic Recording) — a laser heats the media to ~450°C during write so smaller, more stable grains can be written; target ~2 Tb/in² near-term, ~10 Tb/in² long-term. Seagate began HAMR shipments 2024–25 — the key inflection keeping HDDs cost-competitive at high-capacity archival (24 TB conventional, 32–36 TB HAMR).
• MAMR (Microwave-Assisted Magnetic Recording) — WD's alternative energy-assisted path, ~1.3 Tb/in², easier to implement.

The investment consequence is the widening SSD/HDD price-per-bit ratio: through 2025 the ratio widened from ~6.2x to ~16.4x because of the NAND shortage (Tom's Hardware), making hybrid SSD+HDD cheaper relative to all-flash and supporting continued HDD spend in cold-tier hyperscale storage. The "crossover that did not happen" — NAND remains multiples more expensive per bit, so HDDs (extended by HAMR/SMR) hold the bulk cold-archive tier while NAND wins performance-sensitive tiers. The bull case for NAND therefore leans on high-value demand (enterprise/eSSD, KV-cache offload) rather than displacing HDD at the cheapest bulk tier. The countervailing pressure: Kioxia explicitly cites "nearline HDD shortage pushing demand toward high-capacity QLC SSDs" as one of three reasons NAND demand exceeds supply in CY2026.

The NAND interface and SSD-mechanism ladder

How NAND is exposed to the host has its own value ladder, and the climb up it drives enterprise-SSD dollar content:

• SATA III — the legacy SSD interface, hard-capped at ~560 MB/s by the 6 Gb/s PHY (after 8b/10b encoding and protocol overhead). This ceiling is why data-center and performance SSDs migrated off SATA.
• NVMe over PCIe — the modern protocol running directly on PCIe lanes, bypassing legacy AHCI, across Gen3 / Gen4 / Gen5 (each generation roughly doubling per-lane bandwidth): Gen3 ~3.5 GB/s x4 (~50 µs), Gen4 ~7 GB/s (~20–40 µs), Gen5 ~14 GB/s (~15–30 µs). Micron's 9550 PCIe Gen5 holds the read crown at 14.0 GB/s (launched July 2024). NVMe exposes massive parallelism — up to 64K queues with 64K commands each, vs SATA/AHCI's single queue — enabling 3M+ IOPS at sub-100 µs latency.

The KV-cache tiering mechanism (hot in HBM, warm in DDR5/CXL DRAM, cold spilled to NVMe NAND SSD) and the bulk eSSD buildout for training datasets/checkpoints both depend on NVMe-over-PCIe Gen4/Gen5 endurance and bandwidth — turning NAND into an active participant in the inference pipeline. Samsung's PM1753 SSD KV-offload test: 1.7x more concurrent users at equal latency, 1.5x more output tokens/sec under high concurrency, 53% lower total power, ~4% added system cost (I/O pattern 92% reads / 8% writes, 96% of requests >1 MB — suited to SSD sequential-read strengths). High Bandwidth Flash (HBF), co-developed by Sandisk + SK Hynix + Kioxia, is the prospective 2027–28 NAND tier between HBM and NVMe (Sandisk demo: 192 GB HBM → 3,120 GB HBF, 16× density), but cannot replace HBM (µs vs ns latency, ~78 pJ/bit vs 2–3 pJ/bit, endurance limits).

Players

The memory complex is two distinct supplier sets: a tight, consolidated DRAM oligopoly and a more fragmented NAND set. Samsung, SK Hynix, and Micron make both, but the competitive structure differs sharply between the two halves.

DRAM — a tight oligopoly (~95% from three firms)

Three integrated device makers control roughly 95% of DRAM. This is the single most important fact about DRAM: three rational players who all remember the pain of past gluts have strong incentives toward capital discipline.

Maker	Ticker	DRAM share	HBM share	Notes
Samsung	005930.KS	~40% (2024 41% → 2025 34%, −7pp; primer A ~40–45%)	~17% trough (Q2 25) → ~35% (Q3 25)	Scale leader; the HBM laggard. Failed NVIDIA HBM3E 12-layer qualification repeatedly through 2024 (thermal/yield issues), share collapsing ~41%→~17%; finally cleared qual September 2025. 2026 HBM sold out; HBM4 samples delivered, targeting >30% of NVIDIA HBM4. Q4 2025 DS op profit KRW 16.4tn (record); Q1 2026 prelim total op profit KRW 57.2tn (+755% YoY), DS ~95% of it; HBM revenue to triple YoY. V-NAND leader by layer count (Gen 9 286L in production, Gen 10 400L+ announced).
SK hynix	000660.KS	~35% (2024 33% → 2025 35%, +2pp); #1, surpassed Samsung Q4 2024	~62% (Q2 25), down from ~50%+ in 2023	The HBM leader; first to mass-produce 12Hi 36GB HBM3E (Sept 2024); NVIDIA primary. FY2025 revenue KRW 97.15tn (+47%), op profit KRW 47.21tn (49% margin) — all-time record; Q1 2026 op margin 72%; "HBM4 demand exceeds capacity for the next 3 years." TSMC partnership for HBM4 logic base die. NAND via 321L QLC (highest layer count in mass production) + Solidigm. Holds ~14% of Kioxia (voting capped 15% through 2028).
Micron	MU	~24% (2024 21% → 2025 24%, +3pp); #3	~21–24%, overtook Samsung Q2 2025	The only US-based maker (Idaho + Taiwan); CHIPS Act ($6.1B) anchor. HBM3E 8Hi in NVIDIA GB200, 12Hi in GB300 + AMD MI355X; HBM4 36GB 12-high shipping to NVIDIA Vera Rubin from Q1 CY2026, 48GB 16-high sampled; 4 large HBM customers (NVIDIA, AMD, two unnamed). CY2026 fully sold out incl. HBM4. FY2025 revenue $37.08B (DRAM 77% / NAND 23%, GM 40.3%); Q2 FY2026 $23.86B (+196% YoY, GM 74.9%), Q3 FY2026 guide $33.5B. Data center ~56% of revenue. Deliberately cut NAND wafer starts >10%. Pink does NOT hold MU directly (gets indirect exposure via the Roundhill DRAM ETF).

China DRAM newcomer CXMT (ChangXin, Hefei; unlisted, Anhui govt + CITIC) is the credible medium-term threat: ~5% global share (2025, doubled from 2024), targeting ~10% in 2026 at ~300k wpm. At 16nm (1st-gen DDR5) it is 2–3 generations behind Samsung's 1a/1b/1c; gap matters for HBM/advanced DRAM, less for DDR4/entry DDR5. Not yet on the Entity List as of April 2026. Nanya Technology (2408.TW) and Powerchip/PSMC (6770.TW) are small Taiwanese specialty/foundry DRAM players (~1% each).

NAND — more fragmented (six players)

NAND is the lower-margin, more fragmented half. Shares vary modestly between sources (primer estimates A vs Counterpoint revenue-share B).

Maker	Ticker	Share	Notes
Samsung	005930.KS	~33% (A); 2024 33% → 2025 30% (B, −3pp)	Leader; −3pp consistent with deliberate exit from low-margin eMMC/MLC to reallocate to HBM + high-density NAND.
Kioxia	285A (285A.T)	~19% (A); 16% flat (B); Q3 2025 ~15.3%, #2/#3	Ex-Toshiba (co-invented NAND 1987), Japan; spun out via Bain LBO 2018 (~$18B), TSE IPO Dec 18 2024 at ¥1,455. NAND-only — no DRAM, no HBM (pure NAND beta). BiCS8 218L / BiCS10 332L in development; LC9 245.76TB QLC won FMS 2025 Best of Show (KV-cache target). 50/50 Yokkaichi+Kitakami JV with Sandisk (extended to Dec 2034; receives $1.165B from Sandisk 2026–2029).
SK hynix + Solidigm	000660.KS	~20% (A); SKH 11% + Solidigm 8% = ~19% (B)	Solidigm = ex-Intel NAND unit, SK hynix subsidiary (acquired 2021); enterprise eSSD.
Western Digital / Sandisk	SNDK (SNDK)	~13% (A); 12% flat (B)	Sandisk = NAND/flash spun out of Western Digital Feb 24 2025 (reverses the 2016 $19B WD acquisition); WDC retains 19.9% + HDD only. Shares BiCS process with Kioxia via the JV.
Micron	MU	~13% (A); 12% → 13% (B)	Cut NAND wafer starts >10%; QLC data-center penetration is its angle.
YMTC	unlisted (China)	~6% (A, "growing despite sanctions"); 7% → 10% (B, +3pp)	Wuhan, state-backed; US Entity List Dec 2022 + DoD military designation Feb 2024. Despite controls, the +3pp NAND jump is "the most concerning data point in the entire memory complex" for the durability thesis — recurring bear-case supply risk. X4-9070 294L via Xtacking; target ~15% share late 2026.

Ticker linkage — three vault pages (all EXIST; do NOT recreate)

The brief's three wikilinks all have canonical pages already, and the third is NOT a memory maker — correcting an easy mis-identification:

• 285A — Kioxia Holdings (TSE: 285A), page at KB/wiki/285A/285A.md. Status PASS at ¥44,450 (May 15 close); held by Pink (entry ¥35,470); re-engage trigger <¥18,000. The May 15 FY2025 print beat (revenue ¥2,337.6B +37%; non-GAAP op profit ¥876.2B +93.4%) but the NBM/LTA disclosure gap PERSISTS — no formal multi-year contracts/prepayments/minimum revenue, reaffirmed annual "gentleman's agreement" model. Clear laggard on commercial-model transparency vs Sandisk/Micron/SK Hynix/Samsung. Bain Capital selling-down overhang.
• SNDK — Sandisk Corporation (NASDAQ: SNDK), page at KB/wiki/SNDK/SNDK.md. Status HOLD post-Q3 FY26; held by Pink. $1,187 (May 2 2026), ~$176B cap, fwd P/E 7.1× (a ~35× move off the $33 52w low). Q3 FY26: revenue $5.95B (+251% YoY), 78.4% non-GAAP GM, 70.9% op margin, EPS $23.41, FCF $2.96B; $6B buyback. The cleanest NBM disclosure — 5 New Business Model agreements, $42B+ minimum revenue from 3 contracts, >$11B aggregate financial guarantees, >⅓ of FY27 bits locked. Stock fell on the print despite the numbers (durability skepticism). Pink's primary NBM exposure.
• 6871 — Micronics Japan / MJC (TSE: 6871), page at KB/wiki/6871/6871.md. NOT a memory or memory-interface maker — it is a probe-card test-consumable maker (packaging/test layer of the value chain, see value_chain). Top-5 global probe card, #2 in Japan after JEM (6855), HBM-leveraged via KGD test on stacked dies; customers Samsung/SK Hynix/Micron/Kioxia + TSMC/Intel. Status WATCH at ¥13,360 (NOT held); ~$3.5B cap, 48% GM, net cash; re-engage <¥10,500. There is a head-to-head compare page at KB/wiki/_compare/285a-vs-6871-showdown.md (Kioxia the NAND fab vs Micronics the probe-card consumable — same AI-memory thesis, different value-chain layer). My earlier draft wrongly speculated 6871 might be a memory-interface/bottleneck chip — it is the probe-card play, a different (test-consumable) bottleneck.

Other vault pages and named players that LACK a ticker page

Has a page: Macronix (2337.TW) — full deep-dive at KB/wiki/2337/2337.md with KGI initiation (sub-32GB MLC eMMC monopoly thesis); JEM/Japan Electronic Materials (6855.T) — held by Pink, the probe-card peer 6871 is compared against.

Named in the source notes but with NO canonical ticker page in KB/wiki/:

• Samsung (005930.KS), SK hynix (000660.KS), Micron (MU) — the three IDMs, no standalone pages.
• Winbond (2344.TW) — specialty low-density DRAM (sold out through 2027) + global #1 serial NOR.
• Solidigm — ex-Intel NAND, held under SK hynix; no standalone page.
• YMTC, CXMT — China, unlisted/sanctioned; no pages.
• Montage Technology (688008.SS, ~36.8% DDR5 RCD leader), Renesas (~30%), Rambus (RMBS, ~25%) — the RCD oligopoly; Rambus page is a stub (run /deep-dive RMBS), the other two have no page. The key bottleneck-layer plays.
• ISSI (private since 2015, Chinese-owned) — SRAM/specialty memory; Kingston (private) — largest DRAM module maker; FormFactor (FORM), Technoprobe (TPRO.MI), MPI (6223.TW) — probe-card peers; Nanya (2408.TW), Powerchip (6770.TW) — Taiwan specialty/foundry DRAM. No pages.
• AEHR (Aehr Test Systems) — HBM wafer-level burn-in (WaferPak consumable); covered in KB/wiki/themes/burn-in-test-primer.md, buy checklist at AEHR.
• DRAM (Roundhill Memory ETF) — Pink's basket position (inception Apr 2 2026, 0.65% ER; top 5 = Samsung, SK Hynix, Micron, Kioxia, Sandisk). Pink's three memory positions are 285A.T + SNDK + DRAM ETF; she does NOT hold MU directly.

Monitor

Durable dated developments folded from the memory-sector earnings research (compiled 2026-04-26). The raw snapshot stays in briefings/2026-04-26-memory-sector-primer.md. Company-specific earnings facts preserved below as a chronological trail.

Spin-offs, IPOs, structural events

• 2018-06-01: Bain Capital-led consortium closes ¥2 trillion (~$18B) buyout of Toshiba Memory (Asia's largest LBO at the time); acquires ~59.8% (Toshiba retained 40.2%). Tranche 1 (¥960B): Bain lead, SK Hynix (¥266B LP + ¥129B convertible bonds = ¥395B total, ~$3B), Hoya, Development Bank of Japan, INCJ, Mitsubishi UFJ. Tranche 2 (¥440B preferred): Apple, Dell, Kingston, Seagate (supply-security, no voting control).
• 2024-12-18: Kioxia IPO on TSE Prime (delayed from October 2024) at ¥1,455/share; first-day close ~¥1,645 (+13%); IPO market cap ~¥784B (~$5.2B); raised ¥120.4B (~$800M) incl. greenshoe; float ~28% (below TSE Prime 35% requirement); bookrunners Morgan Stanley, Nomura, BofA, Goldman Sachs. Tokyo's largest IPO of 2024. Ticker changed 6600.T → 285A.T. World's #3 NAND maker (~14% global share 2024).
• 2025-02-12: SanDisk separation record date (WDC spin). 2025-02-21: WDC completed tax-free spinoff of flash/NAND business as SanDisk; WDC shareholders received 1/3 SanDisk share per WDC share; SanDisk paid WDC a $1.5B dividend pre-separation; WDC retained 19.9% stake (no consolidation). 2025-02-24: SanDisk begins trading on NASDAQ as SNDK. SanDisk inherits all NAND/SSD products, 50% of Yokkaichi + Kitakami JV with Kioxia, and the BiCS stack. Reverses the 2016 WDC acquisition of SanDisk ($19B).

Micron (MU, fiscal year ends August)

• Q1 FY2025 (Sep–Nov 2024): Revenue $8.70B; GM 39.5%; data center >50% of revenue for first time in company history. HBM revenue >2x sequential, "ahead of plan." NVIDIA confirmed (H200 8-high 24GB HBM3E); second customer named but unidentified.
• Q2 FY2025 (Dec 2024–Feb 2025): Revenue $8.05B; GM ~37.9%. First quarter with HBM revenue >$1B; 50%+ sequential growth; volume shipments to third large HBM3E customer initiated. AMD confirmed (HBM3E 12-high 36GB in MI350X/MI355X). NAND revenue down 20% sequentially; SBU $1.4B (-20% QoQ) — data center customers depleting SSD inventory.
• Q3 FY2025 (Mar–May 2025): Revenue $9.30B; DRAM $7.1B (76%), NAND $2.2B (23%). HBM annualized run rate >$6B; ~50% sequential growth. CEO Sanjay Mehrotra: "HBM is sold out for calendar year 2025... HBM bit demand growth will significantly exceed overall DRAM demand in CY2026." Old-segment detail: CNBU $5.1B (+11% QoQ), Storage $1.5B (+4%), Mobile $1.6B (+45%), Embedded $1.2B (+20%).
• Q4 FY2025 (Jun–Aug 2025): Revenue $11.3B (also cited $11.32B); GM 45.7%. HBM ~$2B/quarter (~$8B annualized). Combined HBM + high-capacity DIMMs + LP server DRAM = $10B for full FY2025 (5x prior year). Data center 56% of full-year FY2025. NAND wafer capacity cut >10% structurally (node transition to 1-gamma). NAND $2.3B despite volume decline (prices up). FY2025 totals: revenue $37.08B, DRAM $28.58B (77%), NAND $8.50B (23%), GM 40.3%.
• Q1 FY2026 (Sep–Nov 2025): Revenue $13.6B; DRAM $10.8B (79%), NAND $2.7B. New segmentation: Cloud Memory BU $5.3B (39%), Core Data Center BU $2.4B (17%); CMBU+CDBU = ~56%. HBM4 volume ramp begins; entire CY2026 supply sold out including HBM4. NVIDIA Vera Rubin HBM4 36GB 12-high confirmed. NAND prices up mid-teens% sequentially. Mehrotra: "Memory is now essential to AI cognitive functions... a strategic asset"; "we are only able to meet about 50% to two-thirds of demand from several key customers." CapEx raised to $20B for FY2026 (up from $18B est.); FY2027 capex to "step up meaningfully" but no meaningful new supply until late 2027 or 2028.
• Q2 FY2026 (Dec 2025–Feb 2026), reported 2026-03-18: Revenue $23.86B (+196% YoY vs $8.05B); DRAM $18.8B (79%), NAND ~$5.0B; GM 74.9%. Business units: CMBU $7.7B (32%, 74% GM), CDBU $5.7B (24%), MCBU $7.7B (32%), AEBU $2.7B (11%). HBM4 48GB 16-high sampled; NVIDIA Vera Rubin primary; price/volume locked for all CY2026. NAND revenue jumped on AI data-center demand for KV-cache SSDs and 122TB high-capacity drives; data center NAND nearly doubled sequentially. CapEx raised to $25B+ for FY2026. Mehrotra: "single-quarter revenue guidance for Q3 FY2026 exceeds the full-year revenue of any year prior to FY2024"; "Agentic AI in PCs and smartphones is doubling memory requirements — AI PCs requiring 32GB vs. the 16GB average."
• Q3 FY2026 guidance: Revenue $33.5B ±$0.75B, GM ~81% (single quarter exceeding any pre-FY2024 full year).
• Named HBM customers (official press): NVIDIA (HBM3E H200, HBM4 Vera Rubin), AMD (HBM3E MI350X/MI355X); third/fourth large customer (one undisclosed hyperscaler) unnamed on calls.
• Product milestones: Micron 9550 PCIe Gen5 SSD launched July 2024 (14.0 GB/s reads, 3.3M IOPS, 43% lower power); 232-layer QLC mass production from April 2024.

Samsung Electronics DS Division (005930.KS, calendar quarters)

• 2024 H1: Ships HBM3 (8-layer) but struggles to qualify 12-layer HBM3E with NVIDIA. Q2 2024 HBM share ~41% (mostly older HBM3); SK Hynix leads HBM3E. SK Hynix first to mass-produce 12Hi 36GB HBM3E (September 2024).
• Q3–Q4 2024: Samsung HBM share drops toward ~17% as HBM3E disqualification creates supply gap; market share at multi-year low.
• Q1 2025: DS revenue KRW 25.1T (~$17.5B); DS op profit KRW 1.1T (~$0.77B). HBM sales down on export controls + NVIDIA qual delay; DS margin collapsed. "AI-related demand expected to remain high in conjunction with launch of new GPUs."
• Q2 2025: DS revenue ~KRW 28T (also cited 27.9T); DS op profit KRW 0.46T (~$0.32B, -90% YoY) — worst DS quarter in years. Driven by (1) US export controls on advanced AI chips to China forcing inventory writedowns, (2) still unable to pass NVIDIA HBM3E 12-layer qualification, (3) elevated fixed costs. NVIDIA HBM3E verification expected Aug 2025. Estimated ~$8–10B lost HBM revenue in H1 2025.
• Q3 2025 (Sept 2025): DS revenue KRW 33.1T (~$23.1B); DS op profit KRW 7.0T (~$4.9B). Passes NVIDIA HBM3E 12-layer qualification; mass production begins; HBM3E to all customers. Announces entire 2026 HBM supply sold out after beginning NVIDIA shipments. HBM share recovers to ~35%. Server SSDs set all-time sales high alongside HBM3E. Kioxia stock rose ~70% in September 2025 (benefits SK Hynix as 14% holder).
• Q4 2025: DS revenue KRW 44T (~$30.8B), all-time record; DS op profit KRW 16.4T (record, nearly the entire FY2024 DS op profit). HBM4 samples shipping to key clients (11.7 Gbps performance). 2026 HBM supply sold out. NAND in shortage; server SSD demand surging; "Key Value SSD for AI inference" called out. "Requests for multiyear supply contracts received from large customers including GPU/ASIC developers and hyperscalers." "Both Samsung and SK Hynix expect memory supply to lag demand through to 2027."
• 2025-12 (mid-Dec): Samsung nears deal to supply >30% of NVIDIA's HBM4 for 2026; HBM4 samples delivered.
• Q1 2026 preliminary (2026-04-07): Consolidated revenue ~KRW 127T (~$94B total company); total operating profit KRW 57.2T (~$38B), +755% YoY; DS estimated ~95% of operating profit. HBM business revenue to triple YoY; HBM4 delivery begins Q1 2026. "Soaring prices for DRAM and NAND combined with strong HBM shipments." "DRAM prices climbed 11 straight months." "NAND tipped into shortage." ~60% of DRAM and NAND shipments absorbed by data center operators. FY2025 DS totals (est.): revenue ~KRW 130.1T, op profit ~KRW 24.9T, ~19% margin.
• FY2023 context: DS full-year operating loss ~KRW 14.9T; company-wide op profit KRW 6.57T (15-year low). Apple supplies 60–70% of iPhone 17 LPDDR5X from Samsung.

SK Hynix (000660.KS)

• FY2023: Revenue KRW 32.77T; op profit -KRW 7.73T (loss, -24% margin) — bottom of cycle.
• Q4 2024: SK Hynix surpasses Samsung in DRAM revenue share for first time (34.4% Q3 → 36.6% Q4). HBM >40% of DRAM revenue (up from 30% Q3 2024).
• FY2024: Revenue KRW 66.19T (+102%); op profit KRW 23.47T (35% margin). HBM share rises to ~62%.
• FY2025: Revenue KRW 97.15T (+47%); op profit KRW 47.21T (49% margin) — all-time record; net profit KRW 42.95T (46.4% net margin). 2025 profit alone exceeded entire 2023 revenue. Highest annual NAND revenue on record (H2-weighted on enterprise SSD/Solidigm). Q4 2025: revenue KRW 32.83T (+63.3% YoY), net profit KRW 15.25T (+90.4% YoY).
• Q1 2026: Operating margin 72%. "HBM4 demand exceeds capacity for the next 3 years." NAND record revenue driven by 321L QLC and Solidigm enterprise SSD.
• SK Hynix holds direct ~14% stake in Kioxia (convertible bonds); via Bain consortium total potential ~34% if all bonds exercised; voting capped at 15% through 2028. Blocked Kioxia-WDC merger in October 2023.

Kioxia (285A.T, fiscal year ends March)

• Q3 FY2024 (Oct–Dec 2024, first post-IPO): Revenue ¥450B (~$3.0B), profitable (¥76.1B profit cited in one source); -31% YoY (trough comparison). "Rapid proliferation of AI... presents an exciting driver for further growth." Full FY2023 actual (Apr 2023–Mar 2024): ¥1.706T ($11.28B), +58.5% YoY; IFRS profit ¥272.3B (~$1.77B). FY2022 had been a loss (op -171, net -243).
• Q4 FY2024 guidance (Jan–Mar 2025): ¥310B guidance; weak; -10.1% YoY; ASPs -20% QoQ; "excess inventory floating around the industry."
• Q1 FY2025 (Apr–Jun 2025): Revenue ¥328B ($2.36B), op profit ¥18.5B ($127.6M); beat ¥310B guidance. CFO Hideki Hanazawa: "clear signs of recovery from the downward trend." NAND ASP +5% QoQ in USD. Segment detail: SSD & Storage ¥217.4B, Smart Devices ¥79.0B, Other ¥46.3B.
• Q2 FY2025 (Jul–Sep 2025): Revenue ¥448.3B (+30.8% QoQ); op profit ¥87.2B (-47.6% YoY but improving). AI demand accelerating; pricing recovery.
• Q3 FY2025 (Oct–Dec 2025), reported ~2026-02-13: Revenue ¥543.6B ($3.56B), all-time record (+21.3% QoQ); net income ¥89.5B (+114.9%/+115% QoQ). All three segments at record highs: SSD & Storage ¥300.4B (+7.8% YoY), Smart Devices ¥186.3B (+59.1% YoY), Other ¥57.0B (+5.2% YoY). Entire CY2026 NAND production sold out. Q4 FY2025 guidance ¥845–935B (midpoint ¥890B vs ¥648B consensus); FY2025 full-year guided ¥2.18–2.27T, net income ¥460–520B. CFO Hanazawa AI quote: "NAND demand projected to exceed supply in CY2026 for three reasons: traditional server replacement cycle, AI inferencing workloads, and nearline HDD shortage pushing demand toward high-capacity QLC SSDs."
• NAND market share: 2024 ~13.8% → Q2 2025 ~13–14% (#3) → Q3 2025 15.3% (#2, moving up past Micron). Technology: BiCS 7 (162L) → BiCS 8 (218L, CBA wafer-bonding, current driver) → BiCS 9 (300+L announced) → BiCS 10 (332L, +9% bit density, 2026 shipments). LC9 245.76TB QLC won "Best of Show" at FMS 2025. Customers (Bloomberg-sourced, unconfirmed on calls): Apple, Microsoft.
• Kioxia–SanDisk JV: transition to compensation-based manufacturing model (SanDisk pays Kioxia per wafer); JV extended through Dec 31, 2034; Kioxia receives $1.165B total over CY2026–2029; Kitakami Fab2 "meaningful output expected H1 2026."

Bain Capital Kioxia selldown timeline

• 2024-12-18: 180-day lock-up begins for Bain, Toshiba, SK Hynix, Hoya. IPO secondary ~12.65M shares at ¥1,455 (~¥18B / ~$123M).
• ~2025-06-15/16: 180-day lock-up expires.
• 2025-11-25: Bain first post-lockup block sale ~36M shares at ~¥9,000 = ~¥355B (~$2.3B).
• Late Feb–early Mar 2026: Bain second block sale ~35–40M shares (est.) at ~¥20,000–25,000 = ~¥700–1,000B (~$3.5B). Bain total realized to Apr 2026 ~$5.7–5.9B; remaining stake at ¥34,580 ~163M shares ~¥5.6T (~$37B); total position realized+unrealized ~$43–44B against the $18B consortium deal. Bain combined stake ~51.06% (Sept 30, 2025 IR) → ~28–30% after two sales. SK Hynix's 15% voting cap expires 2028; Kioxia management targets 35% TSE Prime float by 2030.
• Kioxia financial snapshot: share price ¥34,580 (Apr 24, 2026); all-time high ¥36,870 (Apr 14, 2026); market cap ~¥18.9T (~$126B); trailing P/E ~113x, forward P/E ~7.8x (FY25 guidance). Pink holds at ¥35,470 (also cited ¥35,470 / IPO 23.8x); existing deep-dive = PASS at this level, re-engage <¥18,000.

SanDisk (SNDK, fiscal year ends late June/July)

• WDC pre-spin Q1 FY2025 (Jul–Sep 2024): Cloud = 54% of total WDC revenue ($4.1B total); Flash ~$1.8B est.
• WDC pre-spin Q2 FY2025 (Oct–Dec 2024), call 2025-01-29: Flash $1.9B (flat QoQ, +13% YoY); Cloud 55% of total ($2.3B). CFO: "As inference moves to the Edge... it's going to drive an enormous amount of NAND consumption there." "Flash facing temporary headwinds from NAND pricing pressure / ASP headwinds moderating."
• Q1 FY2026 (Jul–Oct 2025, quarter ended Oct 3, 2025), reported 2026-11-06 [first standalone earnings]: Revenue $2.31B (+21% QoQ, +23% YoY); Data Center $269M (12%, +26% QoQ), Edge $1,387M (61%, +26% QoQ), Consumer $652M (28%, +11% QoQ); non-GAAP GM 29.9% (one source cites 65.2% record non-GAAP — A: 29.9%; B: 65.2%). "Evolving from mobile-centric to data center growth." Five major hyperscale customers active across multiple qualification tracks; BiCS8 TLC PCIe Gen5 qualified at 2 hyperscalers, third in progress. "Customers providing visibility through 2027... multi-quarter volume and price deals."
• Q2 FY2026 (Oct 2025–Jan 2026): Revenue $3.03B/$3.025B (+31% QoQ, +61% YoY); Data Center $440M (14.5%, +64% QoQ, +76% YoY), Edge $1,678M (55.4%, +21% QoQ, +63% YoY), Consumer $907M (30%, +39% QoQ, +52% YoY); non-GAAP GM 51.1% (+18.6 ppts YoY). Data center exabyte growth forecast revised up from mid-20s% to high 60s% for 2026 (AI-driven). "Data center will become the largest consumer of NAND in 2026, surpassing mobile for the first time in 15 years." CEO David Goeckeler on AI mix/enterprise SSD ramp. "Stargate" BiCS8 QLC qualifying at 2+ hyperscalers for KV cache. SNDK up ~295% YTD / ~650% from spin-off price as of April 2026. NAND bit demand growth projected 20–22% for 2026 vs bit supply growth 15–17% (shortage to 2028).
• Q3 FY2026 (reported 2026-04-30) — the durability-debate inflection: Revenue $5.95B (+97% QoQ, +251% YoY); non-GAAP GM 78.4%; non-GAAP op margin 70.9%; non-GAAP EPS $23.41; FCF $2.96B (49.7% margin); CapEx $240M (4% of revenue); net cash position; $6B buyback authorized (no expiration). 5 NBM ("New Business Model") agreements signed (3 in Q3, 2 in Q4 FY26): ~$42B minimum contractual revenue from the 3 Q3 contracts; >$11B aggregate financial guarantees across all 5; $400M prepayments on Q3 balance sheet; >1/3 of FY27 bit shipments locked; max contract duration 5 years; pricing fixed near-term, variable longer-term. Walkaway: prepayment retained + guarantees seized; escrow portion recognized at 100% gross margin. Despite the print, SNDK fell post-earnings on durability skepticism (fixed-pricing trap, flat bit-growth, opaque NBM GAAP recognition). Q4 FY26 guide: revenue $7.75–8.25B, non-GAAP GM 79–81%, non-GAAP EPS $30–33. Pink holds — primary NBM exposure in her book.
• Q3 FY2026 guidance (issued earlier): $4.4–4.8B, non-GAAP GM 65–67%, EPS $12–14.

Macronix (2337.TW) — eMMC monopoly thesis dated points

• 2026-03-12: KGI Securities (Hanhsuan Shen) Outperform initiation; PT NT$300; FY26 EPS NT$30.04, FY27 EPS NT$107.25 (also 107.3). eMMC revenue NT$0.86B (2025) → NT$56.4B (2026) → NT$230B (2027) — 265x in 2 years. KGI math: wafer starts ×17 (FY25 ~1k wpm → 4Q26 8k → 3Q27 17k); bit output/wafer ×2.5–7; ASP/Gb ×7.5 (US$0.07 FY25 → US$0.42 FY26 → US$0.53 FY27). Combined ×35 bit × ×7.5 ASP = ×262 revenue. Q1 2026 contract prices for sub-32GB eMMC up 100–200% QoQ (8GB +183%, 4GB +165%, 16GB +147%).
• 2026-04-17: Collyer Bridge APAC wrap referenced for Macronix.
• 2026-04-19: Morgan Stanley (Tiffany Yeh) Overweight; PT NT$202; FY26 EPS NT$5.90, FY27 EPS NT$19.61 (~1/5 of KGI). MS flagged DDR4 8Gb pricing +60% in 2Q then decelerate into 2H; KV-cache compression called out as a NEW bear factor (server-side software reduces DRAM intensity per workload).
• 2026-04-21: STF Research "Memory Trade After the Memory Trade" + first-principles validation of KGI math; implies ~NT$1,609 at 15x FY27 EPS; identifies 4 risks (3D TLC yield, ASML Immersion DUV delivery, Chinese substitution by GigaDevice+YMTC, Winbond re-entry in 24–36 months = 2028–2029).
• 2026-04-27: STF Q1 2026 call — Dr. Wu: "please forget about AI. eMMC has essentially nothing to do with AI directly" (supply-side driven, not demand-side). Macronix price ~NT$131–132. Consensus FY26 EPS NT$4.59, FY27 NT$8.03, PT NT$176. Stock had run NT$18 → NT$170 (+844%) before settling.

Roundhill DRAM ETF (Pink's basket)

• 2026-04-02: Inception of Roundhill Memory ETF (ticker DRAM, not "DRAMD"). Expense ratio 0.65%; non-diversified. As of ~2026-05-03: NAV $39.15, market price $40.41 (~3% premium — flag as caution). Mandate ≥80% in memory companies with ≥50% revenue from semiconductor memory. Top 5 holdings: Samsung, SK Hynix, Micron, Kioxia, SanDisk (4 of 5 have disclosed NBM/LTA structures; Kioxia the laggard). Korea-concentration risk (Samsung + SK Hynix likely >50% of weight).

Industry-wide / cross-company dated developments

• 2026-04-26: Memory primers and earnings research compiled (this body of research). SemiConSam "Why did the memory chicken game keep repeating" piece argues the chicken-game era is structurally over (DRAM down to Big 3 after Qimonda 2009, Elpida 2012, Micron rolling M&A; further consolidation blocked by Korean/US governments + antitrust); HBM becoming foundry-like via custom HBM (cHBM); LTA spread + "foundry-ization of memory" within two years; "Shouldn't we stop valuing memory companies by P/B now?"
• 2026-05-02: stf Substack note detailing SanDisk NBM walkaway mechanics (escrow recognized at 100% gross margin).
• 2026-05-03: Memory-sector investment brief updated with NAND Durability Debate (NBM/LTA structural shift), basics primer, Pink position sizing. Industry-wide LTA/NBM disclosures: SK Hynix (all 2026 sold out, 10–30% prepayments up from <5% historically, Microsoft + Google named), Samsung DS ("Securing Profit Stability Under Favorable Terms"), Micron (entire 2026 HBM incl. HBM4 committed, FY27/28 negotiations active), SanDisk (5 NBMs). Kioxia has no equivalent customer-side NBM disclosure — flagged information gap. AP Memory: "most important factor to focus on is prepayment from end-customers."
• TrendForce cycle data (Q4 2025 – Q1 2026): NAND prices to jump double digits Q1 CY2026; some products 60%+ contract price hikes (Nov 2025); NAND contract prices +70–75% QoQ (Q1 2026); DRAM contract prices +58–63% QoQ (Q1 2026); conventional DRAM prices surged ~100% in Q1 2026, Samsung lifting Q2 2026 DRAM ~30% QoQ. NAND CapEx to rise only ~5% in 2026 ($21.1B → $22.2B), focus on process upgrades and hybrid bonding not capacity.

Forward watch-list (next 90 days from research date)

• 2026-05-15: Kioxia (285A.T) earnings — first chance to disclose customer-side LTAs and close the gap vs Samsung/SK Hynix/Micron/SanDisk; first chance to address durability.
• ~2026-06: SK Hynix Q2 update (HBM4 contract finalizations + 2027 prepayment disclosures); Micron F3Q FY26 earnings (HBM4 ramp + FY27 commitments).
• ~2026-07 (late): SanDisk Q4 FY26 earnings + FY27 guide — critical first FY27 numerical anchor for the durability question.
• ~2026-08 (early): Macronix Q2 2026 earnings — first real test of eMMC ASP surge translating to revenue and KGI's wafer-in/ASP pass-through assumption.

HBF (High Bandwidth Flash) — dated optionality

• Vik's Newsletter "High Bandwidth Flash: NAND's Bid for AI Memory" (2025-09-22): HBF = NAND tier between HBM and NVMe; SanDisk + SK Hynix + Kioxia co-developing; SanDisk demo 192GB HBM → 3,120GB HBF (16x density); first samples 2H 2026; useful applications 2027–2028; best fit GDDR replacement in prefill compute chips (NVIDIA Rubin CPX). Free option on SNDK + 285A.T post-2027.

Sources

Vault source files folded in (6)

1. /Users/pinks/Dropbox/Wafflebun/KB/wiki/memory-sector-primer.md — Memory Sector Primer (Register D, 2026-04-26): first-principles DRAM/NAND/SRAM/NOR/HDD/SSD/HBM education, AI memory hierarchy, KV cache profit pool, value chain, TAM, cycle position, players, comparative deep dive (Samsung/Micron/Kioxia/SanDisk/Macronix), Kioxia IPO + Bain structure deep dive, FundaAI bull-case assessment.
2. /Users/pinks/Dropbox/Wafflebun/KB/wiki/memory-industry-primer.md — Memory Industry Primer (2026-04-26): company profiles + segment deep-dive (Samsung DS, SK Hynix, Micron, Kioxia, SanDisk/WDC, Macronix, Winbond, ISSI), global NOR flash market structure, non-listed China players (YMTC, CXMT).
3. /Users/pinks/Dropbox/Wafflebun/KB/wiki/themes/memory-sector-brief.md — Memory Sector Investment Briefing (theme, 2026-04-26, updated 2026-05-03): structural story, memory basics primer, competitive landscape, NAND Durability Debate (NBM/LTA), Macronix best-idea thesis, AEHR/RMBS/Kioxia/SanDisk names, HBM demand model, China threat assessment, Macronix + DRAM ETF + HBF implications, Pink's three positions durability scoring. Includes attached audio Recording 20260503183847.m4a.
4. /Users/pinks/Dropbox/Wafflebun/KB/wiki/data-center-memory-types.md — "Why data centers need ten types of memory" (claude-chat, synced 2026-03-08): physics of speed/capacity tradeoff, full hierarchy tour (registers → tape), locality of reference, data-center tiering orchestration (CXL, S3 classes, Meta Tectonic/Baleen).
5. /Users/pinks/Dropbox/Wafflebun/KB/wiki/nand-flash-kv-caching-llm.md — "How NAND flash and KV caching reshape LLM inference economics" (claude-chat, synced 2026-03-08): four-tier memory wall, KV cache scaling math, SSD offload systems (FlexGen, InstInfer, NVIDIA Dynamo, Samsung PM1753), Anthropic prompt caching design + cloud-compute economics.
6. /Users/pinks/Dropbox/Wafflebun/KB/wiki/memory-sector-earnings-research.md — Memory Sector Earnings Research Q1 2024–Q1 2026 (claude-research, 2026-04-26): 8-quarter financial trajectories for MU, Samsung 005930.KS, Kioxia 285A.T, SanDisk SNDK (WDC pre-spin); HBM/NAND/DRAM cycle synthesis; data-gaps caveats. Raw snapshot retained at briefings/2026-04-26-memory-sector-primer.md.

External references cited across the 6 files

Earnings transcripts / IR (Motley Fool, company IR, Business Wire): Micron Q3 FY2025, Q1 FY2026, Q2 FY2026 transcripts (Motley Fool); SanDisk Q1/Q2/Q3 FY2026 results + separation release (investor.sandisk.com, Business Wire 2026-04-30); SanDisk Q3 FY26 transcript (Motley Fool 2026-04-30); Western Digital Q2 FY2025 transcript (Motley Fool 2025-01-29); Samsung Q1/Q3/Q4 2025 results (Samsung Newsroom); Micron Q4 FY2025 prepared remarks (investors.micron.com); Micron FY2025 10-K (stocktitan.net); Kioxia BiCS technology + IPO pages (kioxia.com, Japan Times); SK Hynix FY2023–FY2025 releases (news.skhynix.com).

Research / analyst notes: KGI Securities Macronix initiation (2026-03-12); Morgan Stanley / Tiffany Yeh (2026-04-19); STF Research "Memory Trade After the Memory Trade" (2026-04-21) + STF Q1 2026 call (2026-04-27); STF Substack SanDisk NBM note (2026-05-02, substack.com/@stfbutnou/note/c-252436046); Collyer Bridge APAC wrap (2026-04-17); SemiConSam "Why did the memory chicken game keep repeating" (2026-04-26); Vik's Newsletter "High Bandwidth Flash" (2025-09-22); FundaAI "DeepKioxia: Not a Flash in the Pan"; SemiAnalysis "Scaling the Memory Wall: HBM Roadmap"; Irrational Analysis.

Market-data / news outlets: TrendForce (NAND/HBM/DRAM cycle + market-share data, multiple 2025–2026 press items); Counterpoint Research (HBM + DRAM/NAND revenue share 2024→2025); Omdia (NOR share); Astute Group (HBM share — "SK Hynix holds 62% of HBM"); Futurum (Micron + SanDisk earnings analyses); Time in the Market (Micron Q2 FY2026); Blocks and Files (Kioxia + Samsung coverage); SamMobile (Samsung Q1 2026); KED Global, Digitimes (Samsung HBM4 / CXMT), Neowin (Apple-Samsung memory supply); Tom's Hardware (Micron HBM3E for H200; SSD/HDD price ratio); Yahoo Finance (SanDisk Q2 FY2026); 247wallst (SNDK YTD); Seeking Alpha "Sandisk: Understanding The NBM Issue Behind The Q3 FY26 Earnings Drop" (blocked, accessed via snippets); Mordor Intelligence, Custom Market Insights, Technavio, EE Times (NOR market sizing); Korea Herald, Wikipedia, TechInsights (YMTC/CXMT context).

Technical / academic: FlexGen (ICML 2023); InstInfer (2024); NVIDIA Dynamo (2025); Samsung PM1753 KV-offload whitepaper (2025); Ma & Patterson, Google (Jan 2026, on-chip SRAM limits); FlashAttention; Anthropic prompt-caching docs (Anthropic API / Bedrock / Vertex AI); ngrok / Sam Rose cache-reliability testing; Will McGinnis cost testing (Nov 2025).

Cross-referenced vault pages (wikilinks)

2337/2337.md (Macronix deep-dive + KGI initiation), SNDK, 285A, macronix-kgi-2026-translation, data-center-memory-types, nand-flash-kv-caching-llm, memory-industry-primer, themes/burn-in-test-primer (AEHR/WaferPak), AEHR, themes/intel-supply-chain, china-semi, export-controls-china-semi, agentic-ai-infrastructure-primer, ai-infrastructure, green-finance, _MOC-Semi.

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Consolidation queue (merged 2026-05-30 — section-scoped rebuild)

Industry-wide content folded in from these source files. They stay live pending Pink's review; archive only on her confirm.

• [ ] memory-sector-primer.md
• [ ] memory-industry-primer.md
• [ ] themes/memory-sector-brief.md
• [ ] data-center-memory-types.md
• [ ] nand-flash-kv-caching-llm.md
• [ ] memory-sector-earnings-research.md

Rebuilt 2026-05-30 section-scoped (one agent per section) after a single-agent v1 merge dropped whole themes. Raw dated snapshot retained at briefings/2026-04-26-memory-sector-primer.md.

---

Memory sector primer (folded 2026-06-01, from 2026-04-26-memory-sector-primer)

TLDR

The 2024 to 2026 memory cycle is the first one that is not just a commodity boom and bust. HBM has decoupled from the rest of DRAM and now functions as a long-cycle, contracted, high-margin business sold to NVIDIA, AMD, and the hyperscalers under multi-year supply commitments. SK Hynix posted 49% operating margin in FY2025, an all-time record for any memory maker, almost entirely on HBM3E shipments. Simultaneously, the NAND industry is undergoing a structural consolidation as Samsung, SK Hynix, Micron, and Kioxia all exit sub-32GB MLC eMMC by 2028, leaving Macronix as the only credible global supplier. KV cache offloading is creating a new structural NAND demand tier (122 TB QLC drives at hyperscalers) that did not exist 18 months ago. Sell-side consensus and FundaAI both project shortage through 2027 to 2028, with capex commitments today not delivering wafer output until late 2027 at the earliest. This is a multi-year up-cycle, not a quarter-to-quarter print.

INVESTMENT THESIS — 3 BULLETS

• HBM is the central scarcity. SK Hynix holds ~62% share, Micron ~21-24%, Samsung recovering from ~17% trough after passing NVIDIA HBM3E qualification in September 2025. Entire CY2026 HBM supply already sold out across all three vendors. HBM4 demand exceeds capacity for next 3 years per SK Hynix.
• NAND is undersupplied with a new demand tier. KV cache offloading + 122 TB QLC drives + nearline HDD substitution + AI inferencing add ~5-10% to global NAND demand growth. Industry capex is +5% in 2026 — disciplined. Sandisk gross margin trajectory (29.9% → 51.1% → 65-67% guided) in two quarters proves the operating leverage.
• Macronix is the asymmetric play on NAND consolidation. Samsung exited sub-32GB MLC in October 2025; Micron 2024; Kioxia LTS by 2027. KGI projects Macronix eMMC revenue from NT$0.86B (2025) to NT$230B (2027) — a 265x ramp — with the company as the only credible post-2028 global supplier. NT$300 target = 10x 2026 EPS.

THE PICKS

Rank	Ticker	Conviction	One-Line Thesis	Biggest Risk
1	000660.KS (SK Hynix)	High	HBM near-monopoly, 62% share, 49% FY25 op margin	HBM4 multi-vendor competition 2H 2026
2	MU (Micron)	High	HBM share gainer, NVIDIA Vera Rubin 12-high HBM4 supplier, 56% data center	Samsung HBM4 qualification timing
3	2337.TW (Macronix)	High	Sub-32GB MLC eMMC monopoly post-2028, 265x eMMC revenue ramp	Q1 2026 actuals must validate KGI thesis
4	285A.T (Kioxia)	Medium-High	NAND-only purest play, 7.8x forward P/E	Bain selldown overhang ($3-4B per block sale)
5	SNDK (Sandisk)	Medium-High	Post-spin operating leverage extreme, KV cache QLC qualifying	Already +295% YTD; entry less attractive
6	005930.KS (Samsung)	Medium	HBM3E qualification recovery, HBM4 30%+ NVIDIA allocation target	Diversified, less pure than Hynix
7	688008.SS (Montage)	Medium	DDR5 RCD 36.8% share, IP-like high-margin	China A-share access constraint

Avoid: Western Digital (HDD-only post-spin, no HAMR catalyst yet), Nanya Technology (no HBM, behind Winbond on tech), Powerchip (foundry+DRAM hybrid, China substitution risk).

KIOXIA 285A — BAIN/TOSHIBA LOCK-UP TABLE

Note: Kioxia ticker is 285A.T, not 6600.T as commonly mis-cited.

IPO and entry

Item	Detail
Listing	December 18, 2024 (delayed from October)
IPO price	¥1,455 (midpoint of ¥1,390-1,520)
First-day close	~¥1,645 (+13%)
Total raised	¥120.4B (~$800M) including greenshoe
IPO market cap	¥784B (~$5.2B)
Float at IPO	~28% (below TSE Prime 35% requirement)
Bain entry (2018)	¥2T consortium deal, Asia's largest LBO at the time
SK Hynix entry (2018)	¥395B (~$3B) for ~14% post-conversion stake

Lock-up timeline and selldown

Date	Event
Dec 18, 2024	IPO; 180-day lock-up begins for all major holders
Jun 15-16, 2025	180-day lock-up expires
Nov 25, 2025	Bain block sale #1: ~36M shares at ~¥9,000 = ~¥355B (~$2.3B)
Late Feb-early Mar 2026	Bain block sale #2: ~35-40M shares at ~¥20-25K = ~¥700-1,000B (~$3.5B)
2028	SK Hynix's 15% voting cap on convertible bonds expires
2030 (target)	Kioxia management goal: hit 35% TSE Prime float

Current shareholder structure (April 2026)

Holder	At IPO	Current (est.)	Notes
Bain Capital (BCPE Pangea)	~52%	~28-30%	Two block sales executed; more expected
Toshiba / JIP	~32%	~27-30%	No sales yet; expected to sell down
SK Hynix	~14%	~14%	Voting capped at 15% until 2028
Hoya	~3%	~3%	Stable
Free float	~28%	~28-35%	Rising as Bain sells

Bain economics

Metric	Value
Total realized to April 2026	~$5.7-5.9B
Remaining stake at ¥34,580	~163M shares = ~¥5.6T (~$37B)
Total position value	~$43-44B against $18B consortium deal

Conclusion: There is no price threshold that would cause Bain to hold. Expect another ~5% block sale (~¥480B / ~$3.2B) within 6-12 months. Position size against the supply pressure.

OPEN ITEM — FUNDAAI BULL CASE

FundaAI is extremely bullish on MU, SNDK, and Kioxia 285A for FY2026 EPS, with implied targets ~50-100% above sell-side consensus. The structural thesis is robust (HBM permanent demand, NAND undersupply, pricing leverage non-linear, supply discipline holds, AI accelerator scarcity persists). I'd haircut the EPS bull cases by 20-30% for HBM4 multi-vendor risk and macro tail risk, and weight Sandisk and Kioxia higher than Micron given NAND has the tighter near-term shortage signal and Samsung is a bigger threat to Micron than to Hynix.

Action needed: Chrome session at funda.ai is logged out. Once logged back in, re-run the Estimate Analysis tool on MU, SNDK, 285A.T to pull live FY2026 EPS targets and validate revenue/ASP assumptions against management guidance ranges.

METRICS TO TRACK

Metric	What it measures	Where to find	What's bullish
HBM bit demand growth YoY	Demand for accelerator memory	SK Hynix earnings, NVIDIA capex	>70% YoY through 2027
NAND contract price QoQ	NAND cycle health	TrendForce monthly	+10% or more QoQ sustains thesis
DRAM contract price QoQ	DRAM cycle health	TrendForce monthly	+10% or more QoQ sustains thesis
TSMC CoWoS capacity	HBM packaging bottleneck	TSMC earnings	Capacity expansion lags HBM demand = sustained scarcity
CXMT global DRAM share	China substitution threat	TrendForce	<10% by year-end 2026 = thesis intact
Macronix eMMC bit shipment	Validates KGI thesis	Macronix monthly sales	Q1 2026 print = first real test
Bain Kioxia next block sale	Supply pressure on 285A	TSE filings, JP press	Larger block at lower price = capitulation, buy
HBM4 Samsung qualification	NVIDIA premium compression risk	Samsung earnings	Delay = SK Hynix premium intact

NEXT STEPS

Priority	Command	Why
1	Log into funda.ai in Chrome, then /funda-tools Estimate Analysis on MU, SNDK, 285A.T	Refresh Section 15 with live FY2026 EPS and validate vs sell-side
2	/checklist 2337.TW (Macronix)	Pre-buy discipline before sizing eMMC monopoly thesis
3	/dcf 000660.KS (SK Hynix)	DCF to price the HBM premium, pressure-test the 49% margin extrapolation
4	/mgmt-dd 285A.T (Kioxia)	Standalone management quality vs Bain overhang
5	Watch Macronix Q1 2026 print	First real-world test of KGI's eMMC ramp thesis (NT$0.86B → NT$56.4B in 2026)
6	/profile 688008.SS (Montage)	DDR5 RCD bottleneck deep-dive — IP-like compounder, HK-Connect access
7	Watch for Bain's third Kioxia block sale	Sets supply baseline through 2026; potential entry on capitulation

SOURCE

Full primer at ~/claude/output/primer/memory-sector-primer.md (10,200 words). Built on prior vault research (data-center-memory-types.md, nand-flash-kv-caching-llm.md, Macronix KGI translation), four parallel research threads (memory physics, company financials, Kioxia IPO structure, earnings transcripts last 8 quarters), and SemiAnalysis / FundaAI / KGI / TrendForce sources.