Advanced Packaging & Substrates

Overview / thesis

Advanced packaging and substrates is the layer of the AI build-out where the silicon stops and the system begins. Every AI accelerator — Hopper, Blackwell, Vera Rubin, every hyperscaler ASIC — is a stack of physical layers between the die and the rack: the IC substrate that fans 50,000+ die bumps out to a 4,000-pin BGA, the build-up dielectric and copper that carry the signal across 20-plus layers, the passives that deliver power to each die, the PCB that routes the package across the board, and the optics that escape the copper wall when bandwidth outruns electrical interconnect. The cross-cutting thesis across every source in this sector is the same: the headline names (the GPU, the substrate fabricator, the named PCB fab) are correctly priced or over-priced, and the alpha sits one-to-two layers upstream in the chemistry, materials, equipment, and passive-component tiers that the consensus model still treats as commodity. Each of those upstream layers is a single-vendor or two-vendor concentrated market, each is one bad lot away from halting an Nvidia ramp, and each captures more gross profit per dollar of substrate-fab revenue than the fab itself — at one-tenth the headline revenue and one-twentieth the market cap.

Why it matters now — the demand drivers

The whole sector is being pulled by one physical fact: AI accelerator package area has roughly tripled in two generations, and everything downstream is breaking at the seams. Per STF Research's substrate-area progression, the package goes Hopper 3,025mm² → Blackwell B200 5,625mm² → Vera Rubin 8,100mm² (+86% / +168% vs H100). That single trend cascades into every layer:

• Substrate warpage and signal loss. Organic ABF substrate warps at large panel sizes and its dielectric loss climbs unacceptably at the 224G SerDes generation. Above ~80×80mm warpage is acute; above ~100×100mm it is a yield killer. This is the structural driver of the glass-core substrate transition (see packaging-glass-substrate-primer).
• Build-up layer count. AI substrate layers go 20-24 (Blackwell) → 28-32+ (Vera Rubin), and HDI build-up moves 4+N+4 → 6+N+6. Each step multiplies the per-package consumption of copper foil, ABF resin, and adhesion chemistry — and going 4+N+4 to 6+N+6 is a much bigger production shift than the layer count alone implies.
• Line/space shrink. Fine-line RDL goes 8/8 → 5/5 → 2/2 µm, forcing the transition from standard ED copper foil to carrier foil and from CZ adhesion chemistry to no-roughening AP-series chemistry (see cu-wiring-resin-primer).
• Power delivery integration. 2.5D packaging (Intel EMIB, TSMC CoWoS-S, Samsung I-Cube) integrates multiple dies on a common substrate; each die needs power delivered as close to the silicon as the package allows, which pulls silicon capacitors into the bridge, interposer, and substrate (see silicon-capacitor-primer-2026-05-28).
• Bandwidth wall. Switch bandwidth scales 25.6T → 51.2T → 102.4T → 204.8T; above 51.2T the power and latency of moving bits over copper off the ASIC becomes unacceptable, forcing co-packaged optics next to the die (see sip-osat-rf-primer).
• PCB content per rack. Nvidia Vera Rubin (VR200/VR300) replaces bridge cables with PCBs/CCLs at midplane and backplane (see ai-server-pcb-primer).

The demand is secular, not cyclical in the current phase — set by hyperscaler capex rather than end-consumer purchasing. The single largest risk to the whole sector is hyperscaler capex normalization in 2027+, not near-term cyclicality. The single largest opportunity beyond the named programs is custom hyperscaler silicon — every Trainium, TPU, and Maia generation is a distinct package, distinct substrate, distinct PCB, distinct qualification, distinct revenue stream.

Sizing the opportunity — TAM and growth

The most authoritative sizing across the sources is Goldman Sachs' January 2026 revision (via STF Research), which lifted AI PCB/CCL TAM aggressively:

Market	2027 TAM	Prior estimate	Implied 2025-2027 CAGR
AI PCB	$26.6B	$17.4B	~140%
AI CCL	$18.3B	$8.0B	~178%

The non-obvious wrinkle: CCL TAM grows faster than finished PCB TAM because as layer counts move 24-28 → 40+ and HDI build-up moves 4+N+4 → 6+N+6, industry yield falls from ~73% to ~62%. Lower yield means more raw CCL consumed and scrapped per finished panel — the boards are getting harder to make, and the material tier captures the difference. Growth also accelerates in 2027 vs 2026 (positive second derivative, not a topping pattern). The Vera Rubin content step-ups that drive it: midplane content per GPU rises to ~$171–$256 (107% / 57% jump vs GB300, from 2H26); backplane content per GPU rises to ~$781–$1,563 (5x / 4.5x jump vs GB300, from 2H27).

Broader scope sizing across the sources:

Segment	TAM today	Forward	Notes
Total advanced PCB (AI + non-AI)	$8-10B (2024)	$22-28B (2026E) → $45-60B (2028E)	AI slice CAGR ~140%
Broader PCB (consumer/auto/industrial)	$80-100B	high-single-digit growth	AI slice disproportionate to growth
Glass-core IC substrate	~$0-200M (R&D/qual volume)	$2-5B by 2030	gated on Intel commit + competitor follow
TGV equipment (glass)	~$50-200M (2027-28)	$0.5-1.5B by 2030	top-3 makers >70% share
Premium Cu foil (HVLP/MicroThin)	~$2-3B	scaling with substrate area/layers	Mitsui >90% MicroThin
ABF resin	~$1.5-2B	scaling	Ajinomoto >90%
CZ + adhesion chemistry	~$0.5-1B	scaling, capacity-limited	MEC ~70-100% by sub-tier, 60%+ GM
ABF substrate fabrication	~$15-20B	scaling, cycle-dependent	5-firm oligopoly, fully priced
RF front-end module (packaging slice)	$29B (2025)	$54B by 2030 (~13% CAGR)	content-driven, not unit-driven
Silicon capacitor (SEMCO franchise)	a few $M (2024)	W609bn FY27E / W905bn FY28E	W1.6T 2-yr order anchors

The 'so what' — the recurring investment frame

Every primer in the sector runs the same "bottleneck hunt" and the same "follow the capex" playbook, and they converge on one structural observation. Value capture is split: the substrate fabricator (Ibiden, Shinko, Unimicron, AT&S, SEMCO) owns the customer relationship and the qualification slot; the upstream chemistry, materials, equipment, and passives suppliers own the spec inside that slot. The fabricator tier is cyclical and fully visible to the market; the upstream tier is structurally less cyclical (consumable per panel, not capex-purchased; spec-locked across downcycles; sticky pricing) and earns higher gross margins. The 2024 LITE/COHR pattern — Nvidia EML pre-allocation driving upstream optics +955% — is the explicit template each primer maps onto: trace four derivatives of beneficiary from the Nvidia capex pulse (direct fabricator → near-competitor/alt-supplier → upstream components/tools → second-derivative capex on capacity), and the multibagger lives in the small-cap, single-feature upstream names the consensus model misses.

The per-primer "the $100M-$1B pure-play the market hasn't priced" answers:

• AI server PCB: Fulltech (1815.TW) — LDK/ultra-thin glass cloth, Nittobo's E-glass exit creating a projected 2M meters/month LDK2 gap by 2H26; Kitagawa Seiki (6327.T) — sole vacuum-press supplier qualified for M9/Q-Glass tolerances, 10-yr-high orders.
• Copper wiring & resin: MEC (4971.T) — CZ adhesion chemistry monopoly, highest GM in the stack, AP-series next-platform option unpriced; though all three swarm names (MEC, Ibiden, Mitsui Kinzoku) have already moved 3.4x / 6.7x / 11.8x, so the trade is disciplined re-entry, not initiation.
• Glass substrate: E&R Engineering (8027.TWO) — only public small-cap pure-play with validated TGV laser process, a real option on Intel GlassCore deployment.
• Silicon capacitor / passives: SEMCO (009150.KS) as the only turnkey substrate + silicon-cap bundle for Intel EMIB; AP Memory (6531.TW) on the TSMC/CoWoS side.

The key debates

1. Glass-core substrate timing — 2027-2030 inflection or a perpetual two-years-away. Intel's GlassCore (announced Sept 2023, 2030 production target) is the structural threat to organic ABF. The bull view: package areas now exceed organic substrate's physical limits, the equipment is validated (E&R 2024), Intel is already paying for T-glass as a reported gross-margin headwind (Apr 2026), and the qualification phase is in flight. The bear/risk view: first-line yield is 30-50% versus the 70-80% needed for commercial scale; initial cost is 2-3x ABF; and packaging transitions historically slip 1-3 years from commit to volume. The single leading indicator the sector watches is year-over-year yield improvement at the Japanese substrate maker (E&R's customer). This debate cuts both ways across the sector — glass-core threatens the ABF chemistry tier (Cu foil, ABF resin, CZ chemistry are 3-5 years more durable but eventually displaced at >100mm packages) while creating the glass-material and TGV-equipment opportunity.

2. CPO adoption — has been two years away for five years. Co-packaged optics is the answer to the bandwidth wall, but pluggable optics at 1.6T per channel narrow the power advantage, hyperscalers have paused and restarted CPO programs repeatedly, and TSMC's COUPE program could insource the packaging. The risk case is CPO slips again and the TAM pushes right; the offset is that TSMC capacity is booked through 2026, so first-generation spillover to merchant OSATs (Fabrinet, ShunSin) is probable.

3. Is the upstream alpha already priced? The cleanest tension in the sector. The bottleneck names have outrun the thesis — Mitsui Kinzoku +1,168%, Ibiden +570%, MEC +340%, Victory Giant +600% over twelve months. The cu-resin primer's verdict is blunt: none of the obvious names is mispriced at today's quotes; the trade-from-here is re-entry on pullbacks and being early on the next chemistry transition (MEC's AP series), not initiation. The PCB primer is more constructive on still-under-priced names (Fulltech, Kitagawa Seiki). External validation (Trendforce naming the same nine glass-substrate players the primer already mapped; Zephyr's "silicon caps will pop off like MLCC" PSA) confirms the theses are now widely held — which is itself a signal the easy money has been made on the named layer.

4. Concentration as moat vs. concentration as risk. The same single-vendor structure that gives these names pricing power (Ajinomoto >90% ABF resin; Mitsui >90% MicroThin; MEC ~100% PC-CPU adhesion; Nittobo glass cloth; SABIC ~70% PPO resin) is also the sector's most acute supply risk. The 2020 Ajinomoto Kanagawa fire caused a 90-day shortage; a repeat today halts the AI substrate ramp for a quarter. The April 2026 SABIC PPO outage (25-30% of Saudi capacity lost) was a dress rehearsal. The substrate supply chain is heavily Japanese/Taiwanese/European/US — geographic-decoupling friendly, with Chinese substrate makers barred from US-origin tooling under current export controls.

Structural barriers and switching costs

Across every layer, the moat is the same shape: qualification cycles run 12-36 months, switching a CCL grade takes 6-12 months, switching a PCB fab 12-24 months, switching a glass cloth maker 12-18 months (because the CCL maker re-qualifies the cloth, then the PCB fab re-qualifies the CCL). The chemistry moats are spec-lock, not patent IP — every fab has CZ-8101 written into its qualification document; nobody re-quals the full stack for a 1-2% cost saving. Barrier height does not map to capital intensity: glass cloth has lower capex per ton than a CCL line but the highest barrier, because the know-how is tribal and the qualification window is long. The names that won the smartphone era are not necessarily the names that win the AI era — Victory Giant went from #7 (1.7% global AI/HPC PCB share, 2024) to #1 (13.8%, H1 2025), a 10x share gain in twelve months that only happens during a regime shift.

How it works

Advanced packaging is the layer of the semiconductor stack where heterogeneous components are physically integrated into a single functional module. Modern electronics cannot ship as monolithic chips: a smartphone transceiver needs GaAs power amplifiers, silicon controllers, SAW/BAW filters on lithium-tantalate, and dozens of passives; an AI server needs GPU dies, HBM stacks, networking silicon, and — past 25.6 Tb/s — optical interfaces to escape the copper-interconnect wall. Historically that integration happened on a PCB. For phones it stopped scaling around 2010 (the board got too big, too lossy, too expensive); for data centers it is stopping now (electrical interconnect at 51.2T+ switch bandwidths burns too much power). The answer in both cases is the same: miniaturize the PCB onto a substrate the size of a stamp (SiP), eliminate electrical interconnect by co-packaging optics next to the ASIC (CPO), or rebuild the substrate itself out of a fundamentally more stable material (glass core). This section walks the physics, the process steps, the per-unit economics, and the engineering that creates the moats, from the silicon die down to the PCB.

The vertical stack: die → substrate → PCB

Inside a modern AI accelerator the silicon die is too small and too pin-dense to bond directly to a PCB. Between them sits an IC substrate: a multilayer rigid plate that re-routes the chip's thousands of fine-pitch I/O bumps to the PCB's coarser solder-ball pattern. The substrate is engineered to handle three things at once: huge I/O count (>10,000 contacts on a flagship AI accelerator; the GPU die alone has 50,000-plus solder bumps at 130µm pitch fanning out to a ~4,000-pin BGA ball grid on the bottom), massive thermal load (>1kW per package), and increasingly large physical dimensions (90×90mm and growing). Below the substrate sits the PCB, which routes signals across the rack. Each layer has a different physics problem and a different bottleneck.

An IC substrate is a sandwich. A core sheet (typically 0.4-1.0mm thick) provides mechanical structure. Build-up layers (3-5 on each side; n+N+n notation describes "n build-up layers, N core layers, n build-up layers") carry electrical traces. Through vias connect signals top to bottom. The stack is solder-mask-finished and ball-grid-array attached. The core determines almost everything else: its CTE (coefficient of thermal expansion) has to roughly match silicon (~3 ppm/°C) so the package doesn't fracture under heat; its dimensional stability has to allow ±5µm panel-level alignment over 90mm; its dielectric properties have to support tight impedance control; and the panel size has to allow large packages without warping like a potato chip out of the lamination press.

The dominant substrate today: organic ABF

For three decades the dominant substrate material has been organic ABF — Ajinomoto Build-up Film, a high-performance dielectric resin developed by Ajinomoto and laminated with copper to form multilayer organic substrates. Companies like Ibiden, Shinko, Unimicron, Nan Ya PCB, Kinsus, Simmtech, AT&S, and Samsung Electro-Mechanics convert ABF + glass-cloth core (BT resin or similar) + copper foil into substrates. Hopper, Blackwell, Sapphire Rapids, Granite Rapids all run on ABF.

ABF was tuned for a world of 30-50W CPUs and small packages. AI changed both numbers by an order of magnitude. Organic substrate cores are a glass-cloth-and-resin laminate with CTE ~12-14 ppm/°C and decent thermal stability, but warpage scales with panel size: above ~80×80mm the problem is acute, above ~100×100mm it is a yield killer. The package is now simultaneously a thermal stress test, a mechanical warpage problem, and a high-frequency signal-integrity problem — and organic substrate is approaching its limits on all three axes at once.

The provenance of ABF matters because it explains the moat. Before ABF existed (commercialized by Ajinomoto in the late 1990s) the build-up dielectric was prepreg epoxy: too thick, too high-loss, impossible to drill at the needed resolution. ABF is essentially a B-stage epoxy film with controlled filler loading and a release liner; it can be laminated thin, laser-drilled, and metallized with copper at micron-scale resolution. Ajinomoto solved what was fundamentally a food-chemistry problem (controlled-thickness film extrusion) that happened to apply to substrate dielectrics, and never let it go. ABF holds >90% of advanced organic substrates globally. The deceptive difficulty is uniformity, laser-drillability, and lamination flow simultaneously — every challenger has failed on one of them. Sekisui Chemical's SEKIRES (a low-Dk polyimide film) is the most credible alternative at <5% share and trailing-edge use only; Resonac/Showa Denko makes a photo-dielectric film for RDL fine-line / FOWLP; Kaneka and UBE have low-loss PI/hybrid resins still in R&D.

The substrate build-up flow, sub-layer by sub-layer

The organic build-up substrate is fabricated in a repeating loop. The flow:

1. Core build — glass-cloth-reinforced epoxy (BT or higher-Tg laminate).
2. Drill + plate — mechanical or laser-drilled through-vias, electroplated Cu.
3. Pattern + etch — photoresist-defined copper trace pattern.
4. CZ microetch — surface-prep the Cu before resin lamination (MEC chemistry).
5. Lamination — ABF resin film applied under heat + pressure (Ajinomoto).
6. Laser drill — microvia formation in resin (CO2 or UV laser).
7. Desmear — permanganate clean of resin debris (Atotech/Dow chemistry).
8. Cu seed — electroless Cu deposition (~0.5µm).
9. Pattern plate — photoresist + electroplate to ~15µm trace thickness.
10. Strip + etch — remove resist, etch seed.

Steps 4-10 repeat for each build-up layer (20+ layers for AI accelerator substrates), then solder resist (Taiyo Ink PSR) and ENIG/ENEPIG surface finish (Atotech, Uyemura, Okuno) close out the stack. The yield-killing steps are 4 (adhesion failure → delamination), 6 (drill quality → via reliability), and 9 (plate uniformity → impedance variation). Each is gated by a consumable chemistry sold by a near-monopoly. The fabricator owns the process integration and the customer relationship; the chemistry suppliers own the spec inside the slot. That is why value capture is split.

The three first-principles physics limits of the copper/resin interface

Three physical limits set the engineering space at the layer where AI accelerator signals actually live — the copper-trace-in-resin sandwich.

(a) Skin effect. At GHz frequencies, current does not flow through the bulk of a conductor; it flows in a thin "skin" near the surface. At 28 GHz the skin depth in copper is ~0.4µm. Surface roughness therefore directly costs signal: if roughness is 0.5µm Ra and skin depth is 0.4µm, the effective path length exceeds the geometric path length, and that delta is loss. Lower roughness = lower loss — but lower roughness = worse mechanical adhesion. The chemistry has to thread the needle.

(b) Adhesion physics. Copper-to-resin bond strength comes from two contributions: mechanical interlock (resin keys into surface roughness) and chemical bonding (Cu-O-N or Cu-O-Si linkages depending on resin formulation). At ~0.1µm Ra, mechanical interlock falls off and chemical bonding has to do most of the work. The next-platform chemistry (MEC's "AP series") targets this regime — no-roughening adhesion via a self-assembled molecular layer that creates the chemical bond directly, which is what lets the industry push fine-line RDL below 2µm without losing yield.

(c) Dielectric tan-δ and Dk. Resin dielectric loss (tan-δ) at signal frequency determines insertion loss; dielectric constant (Dk) determines impedance and propagation delay. ABF GZ (current generation) is roughly Dk=3.2 / tan-δ=0.005 at 10 GHz; Vera-Rubin-era substrates need closer to Dk=3.0 / tan-δ=0.003. The losing path to lower Dk is increasing SiO₂ filler loading — that drops Dk but increases laser-drilling difficulty and reduces lamination flow. The winning paths are new resin backbones (cyclo-olefins, low-Dk imides).

The three concentrated material chemistries inside the substrate

The Blackwell B200 substrate is 5,625mm², Vera Rubin's bigger, each carrying 20-plus build-up dielectric layers — every layer a sandwich of copper trace plated into resin. Three single- or two-vendor chemistries gate the whole thing, and each is one bad lot away from halting a substrate ramp:

• The resin — Ajinomoto ABF, the near-monopoly above.
• The copper foil. Cu foil started as electrodeposited (ED) foil in the 1990s when electronics demanded thinner copper than the rolled foil used by the auto industry. For fine-line RDL (2µm features, 1µm thickness), even ED foil is too thick to start with — you need carrier foil: a thin Cu film bonded to a thicker support that gets peeled off after lamination. Mitsui Kinzoku's MicroThin owns this segment at >90% global share. Carrier-foil thickness control (1.5-5µm, uniformity at 0.1µm tolerance over a square meter) is the engineering art; Korean/Chinese H-VLP3 makers are 18-36 months behind on qualification at Nvidia-tier substrate.
• The adhesion. When you laminate copper to resin, the smoothness of the copper surface determines whether they bond at all: too smooth = no adhesion (resin slides off under thermal stress); too rough = signal loss at high frequency (scattering microwaves off random surface features). MEC's CZ-series microetchant etches the copper grain boundaries to a controlled roughness — about 0.1µm at the high end — creating mechanical interlock without destroying signal integrity. Without CZ, the layers delaminate; without controlled CZ, the signal is too lossy for 25+ Gbps SerDes. MEC holds ~100% of PC CPU substrate Cu adhesion and ~70-80% of advanced server/AI substrate adhesion.

The copper-foil tier ladder maps cleanly to product mix — as the substrate node shrinks, the fabricator buys more expensive Cu foil per area:

Tier	Product	Thickness (final)	Use case	Suppliers	Margin profile
Standard ED	Electrodeposited Cu on rotating drum	12-35µm	Standard PCB, low-end CCL	Furukawa, Nippon Denkai, Iljin	Low (~10-15% GM)
Low-profile (LP)	ED, controlled roughness one side	12-18µm	High-speed CCL, server PCB	Mitsui Kinzoku, Furukawa, Iljin	Mid (~25-35% GM)
High-grade VSP/HVLP	Ultra-low-profile, both sides treated	9-18µm	AI server CCL, low-loss substrate	Mitsui Kinzoku (>50% share), Furukawa, Iljin	High (~35-45% GM)
MicroThin carrier foil	Thin Cu on peelable carrier	1.5-5µm	ABF substrate fine-line RDL	Mitsui Kinzoku (>90% share)	Very high (~45-55% GM est.)

The moat at the chemistry layer is spec lock, not patent IP. The CZ chemistry is mostly process-only; every fab has CZ-8101 in its 8-D qualification document, and swapping vendors triggers a full re-qualification cycle (12-24 months per OEM). Nobody does that for a 1-2% chemistry cost-of-goods reduction. That captivity is why MEC sustains 62% gross margins on a small ¥12B revenue base — and also why MEC's growth is rate-limited by capacity expansion, not demand.

Substrate unit economics: where the gross profit actually sits

The investable observation across the substrate sub-layer: the chemistry layer (Cu foil + ABF resin + CZ adhesion) collectively earns more gross profit per dollar of substrate-fab revenue than the fab itself, at one-tenth the headline revenue and one-twentieth the market cap. The profit-pool map:

Layer	Revenue pool (~global)	Gross margin	Concentration	Captures AI cycle?
Cu cathode / smelting	$200B+	5-10% (commodity)	Fragmented	No — commodity wrapper
Premium Cu foil (HVLP/MicroThin)	~$2-3B	35-55%	Single-vendor (Mitsui >90% top tier)	Yes — pricing power confirmed (12% hike, no pushback Apr 2026)
ABF resin	~$1.5-2B	~30-35%	Single-vendor (Ajinomoto >90%)	Yes — but captured at consumer-staples multiple inside conglomerate
CZ + adhesion chemistry	~$0.5-1B	60%+	Single-vendor (MEC ~70-100% by sub-tier)	Yes — but rate-limited by capex
Desmear / EL Cu / surface finish	~$1-1.5B	25-35%	2-3 vendor oligopoly (Atotech, Uyemura)	Partial
Solder resist	~$0.8-1B	30-40%	Single-vendor (Taiyo Ink ~60-70%)	Partial
ABF substrate fab	~$15-20B	25-35% (cycle-dependent)	5-firm oligopoly	Yes — but all of it visible to market

The chemistry tier is structurally less cyclical than the fab tier even though it serves a cyclical end market: chemistry is consumable per panel processed (volume tracks utilization, not fab capex), spec lock prevents switching even in downcycles, and pricing is sticky on the way down (long-term USD-denominated supply agreements, single-vendor leverage). In the 2018-2020 substrate downcycle, fab revenues dropped 25-35% while MEC's CZ revenue dropped <10% and Mitsui's MicroThin volume dropped ~5%.

Substrate technical metrics, today vs next generation

Metric	Today (Blackwell-class)	Next (Vera Rubin-class)	Supplier implication
Line/space (µm)	8/8 typical, 5/5 high-end	2/2 leading edge	MEC AP-series enabling; MicroThin volume rises
Build-up layers	20-24	28-32+	More CZ baths, more ABF film per substrate
Substrate area (mm²)	5,625	8,100+	Cu foil + ABF panel demand scales ~linearly with area
Microvia diameter (µm)	50	35-40	Laser drill capability + resin filler control
Dielectric tan-δ @ 10 GHz	0.005	0.003	Ajinomoto next-gen GZ-N or displacement
Cu surface roughness Ra (µm)	0.1	0.05 or sub-roughening	MEC AP series replaces CZ at flagship tier
ABF film thickness (µm)	25-40	15-25	Ajinomoto formulation + Mitsui MicroThin pairing
Cu foil thickness (µm, post-carrier)	3-5	1-2	MicroThin volume scales; standard ED foil de-mixes

Every column-2 → column-3 step is a chemistry refresh, every refresh is a 12-36-month qualification cycle per OEM, and every qualification cycle is a customer-stickiness event for the incumbent. The substrate-area progression that drives all of this: Hopper 3,025mm² → Blackwell B200 5,625mm² → Vera Rubin 8,100mm² (+86% / +168% vs H100). Each step is 30-50% more material (Cu foil + ABF resin + CZ chemistry) per package.

Glass core substrate: the physics-driven replacement

Organic ABF is hitting three walls simultaneously, and the candidate replacement is glass core substrate: a panel of ultra-flat, ultra-thin glass replaces the organic core. Through-glass vias (TGV) are laser-drilled and metallized to connect top and bottom layers; the substrate is then built up the same way as ABF — but on a far more dimensionally stable, thermally inert, electrically clean foundation. Intel announced its GlassCore program at a September 2023 packaging tech day, targeting glass substrate IC packages by 2030.

The physics is decisive. Glass cores (borosilicate or fused-silica formulations) have CTE ~3 ppm/°C — matched to silicon (vs 12-14 for organic), dimensional stability extraordinary, surface flatness to <1µm RMS, and dielectric loss far lower than organic at high frequency. Glass solves the three problems organic hits at once: thermal-cycling fracture, panel warpage, and 224G-SerDes-generation signal loss.

The catch is that glass is brittle, which is why it took 30 years. You cannot drill mechanical holes without micro-cracking; standard photolithography is hard because the surface is too smooth; plating chemistry has to be invented; singulation requires laser scoring plus breaking. The end-to-end flow: glass material → panel cutting and surface prep → TGV laser drilling (E&R, LPKF) → via metallization (CVD/PVD copper seed + electroplating; Applied Materials, Lam, Tango) → repeated dielectric build-up + copper imaging + cure → solder mask + surface finish + electrical test → singulation via laser score + break (Disco, E&R) → final inspection → die attach.

Where the glass-core engineering challenges concentrate:

1. TGV drilling — the hardest single step. Glass cracks under mechanical force, so vias are drilled with ultrafast lasers (femtosecond to picosecond pulses). Each via is 50-100µm diameter, drilled through 0.4-1.0mm of glass, with sub-µm positional accuracy. A typical AI substrate panel has 100,000-500,000 TGVs. Throughput, yield, and via-wall quality determine commercial viability.
2. Via metallization — TGVs need conformal copper plating end to end. Walls are smoother than organic vias (good for uniformity) but the high aspect ratios (10:1 to 30:1) push electrochemical deposition to its limits.
3. Surface adhesion — build-up dielectric must bond to glass and to copper-on-glass; surface activation (plasma + silane coupling) must be developed per glass formulation.
4. Thermal management during build-up — lamination cycles run 180-220°C, but glass and the build-up dielectric have different CTEs, creating warpage on cooldown. Process tuning is empirical.
5. Singulation without cracking — 510×515mm panel-level singulation via laser score + mechanical break; crack propagation at edges is a yield killer.
6. System-level yield — product yield is the product of all step yields. First-production-line yield is estimated at 30-50%, far below the 80%+ needed for commercial scale (target >70% by 2027). Yield is the single metric gating deployment.

Glass core is not a 1:1 port of organic know-how — substrate makers must rebuild their process libraries, which is what creates the share-shift opportunity (incumbents do not automatically win the next generation). It also unlocks larger panel-level packaging because the substrate itself is dimensionally stable, which in turn enables larger packages (Vera Rubin's 90×90mm+) and more co-packaged die (3D stacking, chiplet integration, integrated photonics). Glass substrate is an enabling layer, not just a material substitution.

Glass formulation variants:

Type	Composition	CTE	Notes
Borosilicate	Boron + silicate base	~3-5 ppm/°C	Mainstream candidate; workable, reasonably priced
Fused silica	Pure SiO₂	~0.5 ppm/°C	Lowest CTE, highest thermal; expensive, hard in large panels
T-glass / specialty	Engineered low-CTE blends	tunable	Proprietary recipes (Nittobo T-glass etc.); low-CTE specialty for substrate cores
Q-Glass	High-performance grade for AI substrate	tightest tolerances	Limited supply; flagged as Vera Rubin generation material

Architecture variants: all-glass core with organic build-up (the most common Intel GlassCore reference — glass for the dimensionally hard parts, organic for build-up where glass would be over-engineered); glass-core + glass-build-up (long-term target, not deployed); and hybrid glass+organic sandwich (transitional demonstrators). Glass substrate also displaces some PCB content — the highest-frequency routes migrate up into the substrate — and its dielectric properties are favorable for in-substrate photonic integration and for HBM4+ packaging where low CTE helps very high stack heights. Cost premium is the headwind: initial deployment is likely 2-3x ABF substrate cost, and the threshold for mainstream replacement is convergence to roughly ABF + 30-50% premium.

Glass-core vs organic manufacturing, step by step:

Step	Organic ABF	Glass core
Core production	Glass-cloth + resin lamination	Glass-panel manufacture (different industry)
Via formation	Mechanical or laser drill	Laser drill only (no mechanical option)
Via plating	Mature	Newer; higher-aspect-ratio constraints
Build-up	25+ years of process maturity	Fresh process development
Singulation	Punching or routing; mature	Laser score + break; immature
Equipment ecosystem	Widely available	Concentrating to <10 qualified suppliers globally

The glass-core key metrics: Core CTE 12-14 → 3-4 ppm/°C; surface roughness 0.3-0.5 → <0.1µm RMS; panel-level warpage @100°C 200-400µm → <50µm over 100mm; max panel size ~510×515mm → 600×600mm+ feasible; dielectric loss @ 56GHz Df ~0.005 → <0.001; TGV aspect ratio 10:1 today → 20-30:1 target.

Silicon capacitors: power delivery inside the package

As AI accelerators move to 2.5D packaging (Intel EMIB, TSMC CoWoS-S, Samsung I-Cube) that integrates multiple silicon dies on a common substrate, each die needs power delivery integrated as close to the silicon as the package allows. MLCC on the PCB is too far; even MLCC on the package top is too far for the highest-frequency rails. A silicon capacitor solves this by sitting embedded in the bridge, interposer, or ABF substrate.

A silicon capacitor is a chip-form capacitor fabricated on a silicon wafer using semiconductor lithography and etching: trenches are etched into silicon to maximize surface area, coated with a high-permittivity dielectric (Al₂O₃ or HfO₂ via atomic layer deposition), then metallized. The result is a passive that behaves more like a tiny silicon die than a ceramic capacitor.

Against MLCC, the silicon capacitor wins on ultra-thin form factor (80-100µm vs 200-1,000µm for MLCC), ultra-low ESL (<0.1 nH vs 0.3-1 nH), and effective frequency response above 1 GHz (vs ~100 MHz for MLCC). It loses on cost ($0.10-1 each vs $0.001-0.10 for MLCC) and maximum capacitance (mostly <100 nF vs up to 220µF in 1206-size MLCC). It does not replace MLCC in volume — it complements MLCC in three specific places: ultra-high frequency, ultra-thin packaging, and embedded-in-substrate.

The supply side is four qualified makers: Murata (acquired IPDiA 2016, Caen, France), Samsung Electro-Mechanics (in-house), AP Memory (Taiwanese, TSMC fab partnership), and TSMC itself (Integrated Passive Devices on advanced nodes). Murata and TSMC have internal demand from their own packaging, leaving SEMCO and AP Memory as the merchant suppliers with most addressable external order book. AP Memory's two product lines illustrate the form factors: discrete S-SiCap IPD (Gen3 in production, Gen4 ramping 2026) and a silicon-capacitor interposer IPC (four-reticle mass production from end-Q3 2025), with CoWoS-S (IPC) + CoWoS-L (IPD) adjacency at TSMC being additive.

The structural reason silicon capacitors only now became a real merchant market: TSMC, which holds an overwhelming share of AI-packaging substrates, historically sourced silicon capacitors in-house, making it effectively impossible for outside suppliers to break into the AI-packaging value chain. The rise of Intel's EMIB changed that — Intel cannot make its own silicon capacitors and must source them externally. Within the Intel EMIB BoM, the highest-value-added component is the substrate; a supplier that can deliver both substrate and silicon capacitor on a turnkey basis maximizes its bargaining power. SEMCO is the only company in the world that operates both a silicon capacitor business and a substrate business — the turnkey bundle is the moat, one that Murata (allied to Ibiden) and AP Memory (allied to TSMC) cannot structurally match. The demand step-change is driven by three design wins: Google v8e TPU (2H 2027 launch, EMIB with embedded silicon capacitors), Intel EMIB scale-up from 2027 (covering Microsoft Maia, Amazon Trainium, NVIDIA networking, Intel's own products), and Amazon Trainium/Inferentia pulling silicon-cap content via Intel.

SiP — system-in-package

A SiP is a laminate or silicon substrate, ~5×5mm to 20×20mm, carrying multiple dies of different technologies (flip-chipped or wire-bonded) with SMD passives mounted alongside, encapsulated in epoxy molding compound. To the outside world it presents as a single "chip" — solder bumps or LGA pads on the bottom. Canonical products: RF front-end modules (GaAs PA + silicon controller + filters + matching networks, BOM $3-8/module), Wi-Fi FEMs (BOM $1-4), wearable SiP (SoC + memory + PMIC + BT + sensors, e.g. Apple's S-series assembled by USI), and sensor modules (MEMS + ASIC + filter).

SiP wins over the PCB-equivalent because it is smaller (3-5× density), faster (shorter traces between dies, less parasitics), cheaper at volume for heterogeneous workloads (you cannot fab a PA and a CMOS controller on the same wafer), and faster time-to-market (dies from different fabs and generations). The cost: thermal management (no heat spreader), yield compounding (multiple dies multiply scrap risk), and test complexity. Key metrics: module footprint (Wi-Fi 7 flagship FEMs converging on ~25mm²), yield after final test (90-97% for mature SiP), thermal dissipation (PAs dissipate 4-8 W/cm² steady-state), and RF performance (insertion loss at band, P1dB compression, ACLR linearity).

RF front-end modules

RF content per smartphone has risen from ~$15 BOM in the 4G era to ~$35-40 in the 5G + Wi-Fi 7 + UWB + satellite era. The TAM is $29B in 2025 projected to $54B by 2030 (13% CAGR). Crucially this is content growth per device, not unit growth — handset units are flat. The packaging/OSAT layer takes a slice of every RF module BOM. The IDMs (Skyworks PAD modules, Qorvo antennas/diversity/envelope-tracking, Broadcom FBAR filters, Qualcomm-TDK RF360, Murata SAW/BAW) do most packaging in-house, so merchant OSAT captures only secondary sockets and overflow capacity.

OSAT — the contract manufacturer of integration

OSATs (outsourced semiconductor assembly and test) buy dies from fabs, substrates from substrate makers, lasers and filters from specialty IDMs, and assemble finished modules under contract. The layer has three sub-markets with margins rising left to right: commodity OSAT (wirebond, leadframe, flip-chip BGA, ~12% GM — ASE, Amkor, JCET), specialty SiP/RF (~15-18% — USI, Amkor auto SiP, ShunSin, Nepes), and optical/silicon-photonics (20-30%+ — Fabrinet, ShunSin FAU attach). OSATs run capex/revenue of ~10-15% in normal years, 20%+ in cycle-up years; a modern advanced-packaging line costs $100-300M; qualification cycles with hyperscalers take 12-18 months; and switching an assembler mid-program is a 6-9 month requalification, making switching costs extreme. The single biggest OSAT-level capex event is ASE's CoWoP (CoWoS-on-PCB) and the CoWoS capacity tripling (~20-25k wafers/mo by end-2025); TSMC CoWoS is booked through 2026, so spillover to merchant OSATs is probable. The advanced-packaging frontier — 2.5D/3D, FOWLP, CoWoS-class — is largely TSMC-insourced plus ASE + Amkor, with Japanese specialty (Shinko, NTT AT) in interposers.

Silicon photonics & CPO — the data-center inflection

AI data-center switch bandwidth is scaling 25.6T (shipping) → 51.2T (2024-25) → 102.4T (2025-26) → 204.8T (2027-28). At 51.2T and above, the power and latency cost of electrical interconnect off the switch ASIC becomes unacceptable — the wire on the PCB drinks too much energy just to move bits 30cm. The fix is to move the optical engine next to the ASIC (co-packaged optics, CPO).

The governing physics: electrons are cheap to switch but expensive to move; photons are expensive to generate but essentially free to move. Silicon-photonics transceivers use standard CMOS wafers patterned with waveguides and Mach-Zehnder modulators to modulate light at 100+ Gbps per lane. External InP lasers (silicon is a poor light emitter) are coupled into the chip. Per-bit energy today is ~5 pJ/bit; target <1 pJ/bit by 2028. The hard parts:

1. Laser attach — flip-chip InP laser dies onto the SiPh substrate with sub-micron alignment. Yield-limiting.
2. FAU (Fiber Array Unit) attach — align multi-channel fiber arrays to silicon waveguides at sub-micron precision; 200nm misalignment costs 1 dB of insertion loss. The single highest-skill step in optical packaging.
3. Thermal control — ring-resonator modulators drift 80 pm/°C, needing micro-heater feedback loops.
4. Hermetic seal — the optical path must be sealed from contamination for long-term reliability.

CPO economics: a 51.2T CPO module integrates ~64× 800G channels, finished module ASP $3,000-5,000, assembly/test margin capture 20-35% GM at scale. One CPO module replaces 32 pluggables on a faceplate, so per-channel volume is smaller than pluggable, but per-unit dollar content is much higher and the process is harder — fewer houses can do it. The adoption risk is real: CPO has been "2 years away for 5 years," pluggables at 1.6T per-channel narrow the power advantage, and hyperscalers have paused and restarted programs. TSMC's COUPE (Compact Universal Photonic Engine) is the insourced-at-TSMC SiPh play combining SoIC and photonics; if TSMC captures CPO packaging at scale the merchant OSAT opportunity shrinks, but TSMC capacity is constrained so first-generation spillover is probable.

The PCB layer below the substrate

A PCB is a sandwich: layers of copper foil separated by glass-cloth-and-resin insulation, glued under heat and pressure, then drilled and plated. Two sheets of woven fiberglass cloth impregnated with epoxy resin, with copper foil pressed on each side and heat-cured, make a copper-clad laminate (CCL) — the raw material of every PCB. To turn CCL into a PCB you (1) pattern the copper, (2) stack and laminate multiple patterned layers between prepreg bonding sheets, (3) drill thousands-to-tens-of-thousands of holes (mechanical ≥0.1mm via Union Tool/Tungaloy/Kyocera drills + Schmoll/Posalux machines; laser ≤0.1mm via Mitsubishi Electric CO2 / Via Mechanics UV for HDI microvias), (4) plate copper onto hole walls (plated through-holes, or microvias for HDI), and (5) finish with solder mask, surface finish (ENIG/immersion silver/OSP), test and depanel. Conceptually a PCB factory is a machine shop with an electroplating line bolted to a chemistry lab. The reason an AI server PCB is hard is not that the steps differ — they are the same — but that tolerances at every step are 10-100x tighter than a smartphone board. An AI server board consumes 30,000-50,000 mechanical holes plus 200,000-500,000 microvias per panel.

Four physical limits drive the entire PCB industry structure:

1. Insertion loss. Every centimeter of trace attenuates signal. At 28 GHz (PCIe 6.0, NVLink 5) across a 50cm trace the loss budget is brutal — you need a CCL with Dk ~3.0-3.5 and Df <0.002. Standard FR-4 (Dk ~4.5, Df ~0.02) is unusable. The materials that qualify — Panasonic Megtron 6/7/7N/8, Rogers RO4000, Shengyi S7460, ITEQ IT-988GSE — all use low-Dk glass cloth (LDK1, LDK2, sometimes T-glass) plus PPO/PPE-based resin (SABIC NORYL) or BT (Mitsubishi Gas Chemical). This is why the materials supply chain matters more than the fab.
2. Layer count. More layers = more parallel signal paths. AI accelerators need 80-120+ HBM lanes and 18+ NVLink lanes per GPU; switches need 64+ 800G ports. AI server motherboards run 20-30 layers, NVSwitch trays and OAM baseboards 40-50+. Each layer roughly doubles fab complexity because lamination is sequential with intermediate inspection.
3. Via density and aspect ratio. A 1mm board with a 0.1mm via is aspect ratio 10:1 — at the limit of copper plating. AI boards push to 20:1 and 30:1, requiring HDI with stacked/staggered microvias and anylayer HDI (every layer can microvia to any adjacent layer). Fewer than ten fabs worldwide can deliver anylayer HDI at AI server volume and yield.
4. Yield × area. Yield × board area = effective output. A fab yielding 95% on a 600mm² phone board can yield 60% on a 2,500mm² AI server board because defect probability scales with area. Share leaders are whoever has the highest yield — which is process know-how, empirical not theoretical.

PCB yield economics, simplified: a smartphone board (8 layers, 100% yield baseline, $5 ASP, $1.50 cost) lands ~70% gross margin; an AI server motherboard (30 layers, 60% effective yield, $1,200 ASP, $300 marginal cost at 60% yield) lands ~75% gross margin for the boards that ship, plus a 40% inventory write-off on scrap. The AI board generates ~5-7x the gross profit per panel-equivalent even after yield loss because ASP scales faster than cost — which is why every Asian fab is racing to qualify on AI programs. A non-obvious wrinkle drives the materials tier: as layer counts move 24-28 (2025) → 40+ (2027) and HDI build-up moves 4+N+4 → 6+N+6, industry yield falls from ~73% to ~62%. Lower yield = more raw CCL consumed per finished panel, so CCL TAM grows faster than finished-PCB TAM (178% CAGR vs 140% per the Goldman Sachs January 2026 revision).

CCL material grades and their loss specs:

Material	Application	Dk @ 28GHz	Df @ 28GHz	Cost / sqm
FR-4	Consumer, low-end	~4.5	~0.020	1x baseline
Megtron 6	High-speed networking	~3.7	~0.005	4-5x
Megtron 7 / 7N	AI accelerator boards	~3.4	~0.003	8-10x
Megtron 8 / Tachyon 100G	Next-gen 224G SerDes	~3.0	~0.0015	12-15x
BT resin substrate	IC substrate	~3.4	~0.005	20-30x (substrate, smaller area)
ABF film	High-end IC substrate	n/a (dielectric film)	n/a	premium

Material grade and supplier are tied: M7/M7N is Panasonic-dominant (Shengyi, EMC alternates), M8 essentially Panasonic alone with Shengyi catching up. Each grade step (Megtron 6 → 7 → 7N → 8 → M9) is a 12-18-month qualification event that reshuffles supplier rankings — a multi-year share-shift, not a one-time swap. Mechanical and laser drilling both scale: mechanical with layer count (more holes per board), laser with HDI density (more microvias per board).

The PCB material bottleneck: glass cloth and resin

The PCB profit-pool map shows the alpha is two layers upstream of the named fabricators:

Layer	Revenue pool '26E	Gross margin	Concentration	Where alpha lives
Raw materials	$5-8B	25-35%	Medium (SABIC dominant in PPO)	SABIC outage = priced
Glass cloth / Cu foil	$8-12B	30-50%	High — top 3 glass cloth ~70%	Yes — Nittobo/Fulltech bottleneck
CCL	$25-35B	25-35% premium / 15-20% standard	Medium-high	Yes — premium CCL squeeze
PCB fabricators	$80-110B	25-40% advanced / 12-18% commodity	Medium	Partial — share-shift play
Equipment / consumables	$5-8B	35-45%	High (Union Tool, Mitsubishi)	Already priced
ODM	$300-400B	4-8%	High (Foxconn)	No pricing power

The single most under-priced layer is high-end glass cloth: small revenue pool but margin expanding fast and top-three players control 70%+. The supply curve has gone vertical because of two simultaneous shortages. First, Nittobo — the world's most important fiberglass cloth maker — is exiting ultra-thin high-end E-glass to focus on LDK and T-glass for IC substrates. This is a structural capacity withdrawal, not a routine mix shift: every CCL maker downstream (Shengyi, Panasonic, ITEQ, Elite, Victory Giant, Unimicron, Ibiden) depends on this cloth. E-glass thin-fabric prices rose ~30% YTD as of April 2026 with participants pricing another doubling in 2026, and a 2 million meters/month LDK2 supply gap by 2H26 is forecast. Second, SABIC — which controls ~70% of world PPO resin supply — lost 25-30% of its Saudi capacity in mid-April 2026 to a natural-gas constraint. PPO is the resin in low-loss CCL, so reinforcement (glass cloth) and matrix (PPO resin) are short simultaneously in the laminate that goes into every AI server board.

Barrier height in PCB does not map to capital intensity: glass cloth has lower capex per ton than a CCL line, but qualification cycles and tribal know-how make it the highest-barrier tier. Switching a CCL grade in a qualified design takes 6-12 months of re-testing with the end customer; switching a PCB fab takes 12-24 months for an AI accelerator board; switching a glass-cloth maker can take 12-18 months because the CCL maker must re-qualify the cloth, then the PCB fab must re-qualify the CCL. These are real, multi-quarter switching costs that give each layer pricing power once a customer locks in. The CCL and glass-cloth tiers are driven by lagging supply additions — every cycle of PCB demand growth triggers a 12-24-month delayed addition of cloth/CCL capacity, so the current tightness lasts longer at the materials tier than at the fab tier.

The equipment bottleneck has its own physics: as Vera Rubin moves to M9 + Q-Glass ultra-low-loss materials, the processing window narrows dramatically — vacuum-press tolerances and lamination cycles for M9/Q-Glass are tighter than anything in production, which is why Kitagawa Seiki (world #1 vacuum press for CCL/multi-layer lamination) is the sole supplier qualified for M9/Q-Glass tolerances and its order intake hit a 10-year high. The solder-mask layer is similarly inflecting: Rubin substrate moves to 100% dry film (vs Hopper's mostly-liquid ink; B200 dry-film attach rate jumped 50% → 90%), and dry film carries a 30-50% ASP premium over liquid ink, while FPIM (Fine Pitch Insulating Material) — co-developed with imec — enables Rubin's <2µm RDL on the HBM4 logic base die.

The PCB demand build

The Goldman Sachs January 2026 revision sets the quantitative anchor: AI PCB TAM $26.6B in 2027 (up from $17.4B), implied ~140% CAGR 2025-2027; AI CCL TAM $18.3B in 2027 (up from $8.0B), implied ~178% CAGR — and growth accelerates in 2027 vs 2026 (the second derivative is positive). The driver is NVIDIA Vera Rubin (VR200/VR300), which replaces bridge cables with PCBs/CCLs at the midplane and backplane: midplane content per GPU rises to ~$171-256 (107%/57% jump vs GB300 NVL72) from 2H26, and backplane content per GPU rises to ~$781-1,563 (5x/4.5x jump vs GB300) from 2H27. Total advanced PCB (AI + non-AI advanced) was ~$8-10B in 2024, growing to ~$22-28B in 2026E and toward ~$45-60B by 2028E. The broader PCB market (consumer/auto/industrial) is ~$80-100B growing high-single-digits, so the AI/HPC slice is disproportionately important to growth even as a minority of revenue.

The PCB segment catalog spans: OAM/UBB accelerator baseboards (22-30 layers, anylayer HDI, Megtron 7/7N, ~600×400mm panel, ASP $2,000-5,000); NVSwitch/network switch trays (30-50+ layers, Megtron 8, lowest-loss requirement of any board, ASP $5,000-15,000, handling 1.8 TB/s NVLink); compute/CPU baseboards (16-22 layers, Megtron 6, ASP $500-1,500); power/converter PCBs (8-16 layers, heavy copper 3-6oz, 48V→0.8V step-down, ASP $200-500); IC substrates (4-2-4 to 8-2-8 build-up, ABF dielectric, T-glass core, ASP $50-300, >100M units/yr); and optical-module/CPO PCB (12-20 layers, Megtron 7/7N, very tight impedance).

Why the moats are durable across every layer

The recurring structural facts that create defensibility, layer by layer: glass material is produced at scale by only 4-5 firms globally; TGV equipment requires femtosecond/picosecond laser process know-how plus a 3-5-year customer qualification engagement; substrate fabrication requires end-to-end process libraries that cannot be ported from organic to glass 1:1; the substrate chemistry layer (ABF resin, MicroThin foil, CZ adhesion) is single-vendor spec-locked into every fab's qualification document; PCB anylayer-HDI yield is empirical craft accumulated over 15-20 years; glass cloth and CCL carry 12-18-month qualification cycles. Across the entire stack the same pattern holds — the barrier is qualification time and process know-how, not capital, and once a customer qualifies a supplier for a specific program the switching cost runs 6-36 months, creating structural lock-in for early movers and a multi-quarter pricing-power window for whoever owns the spec.

For company-specific positioning and deep-dives see 8027 (E&R / TGV laser), LPKF, 4971 (MEC / CZ chemistry), 5706 (Mitsui Kinzoku / MicroThin), 4062 (Ibiden), ATS (AT&S), 6531 (AP Memory), 5201 / 5214 / 7741 (AGC / NEG / Hoya glass triad), and the companion primers ai-server-pcb-primer, packaging-glass-substrate-primer, cu-wiring-resin-primer, and sip-osat-rf-primer.

Subsectors

Advanced Packaging & Substrates is not one industry. It is a stack of physically adjacent layers — die, substrate, board — each with its own supply chain, its own bottleneck, and its own set of public-market plays. The unifying driver across all of them is the same: AI accelerator packages have grown an order of magnitude in area, power, and I/O count, and every layer of the stack is hitting a physical wall at the same time. The subsectors below run top-to-bottom through that stack, plus the passive and assembly subsectors that sit alongside it.

A quick orientation on where each subsector physically lives: the silicon die sits at the top. Below it, an IC substrate (today organic ABF, tomorrow possibly glass-core) re-routes the die's fine-pitch I/O to the coarser PCB. Inside and around that substrate sit silicon capacitors (embedded power delivery) and SiP / RF / photonic modules (heterogeneous integration). One layer below the substrate fabricator is the copper-wiring + resin sub-layer — the actual metal-and-dielectric interface where signals live. Below that again is the CCL / glass-cloth materials tier feeding both the substrate and the AI server PCB. The investment pattern that repeats across every layer: the named beneficiary (the fabricator, the module house) is usually well-priced; the alpha sits one or two layers upstream in a concentrated, single-vendor consumable or material tier the market has not yet re-rated.

Glass-core / TGV substrates

What it is. A proposed replacement for organic ABF substrate: a panel of ultra-flat, ultra-thin specialty glass replaces the organic core, with through-glass vias (TGV) laser-drilled and copper-metallized to connect top and bottom build-up layers. Intel branded its program GlassCore at a September 2023 packaging tech day, targeting glass substrate IC packages by 2030. This is distinct from PCB-level glass cloth, from Hoya's photomask glass, and from smartphone cover glass — a separate industry and supply chain.

Why now. AI accelerator package areas are at the edge of organic substrate's physical limits. Per STF Research's substrate-area progression: Hopper substrate 3,025mm² → Blackwell B200 5,625mm² → Vera Rubin 8,100mm² (+86% / +168% vs H100). Organic ABF warps at large panel sizes and signal loss climbs unacceptably at the 224G SerDes generation. Glass core fixes both because glass solves three problems organic substrate hits simultaneously: CTE matched to silicon (~3 ppm/°C vs organic 12-14), surface flatness <1µm RMS, and dielectric loss far lower at high frequency (Df <0.001 target vs organic ~0.005 at 56GHz).

The technology. The core determines almost everything else — CTE has to roughly match silicon (~3 ppm/°C) so the package doesn't fracture under heat. Glass cores are borosilicate or fused-silica formulations. The catch is that glass is brittle: you cannot mechanical-drill it without micro-cracking, so vias must be laser-drilled with ultrafast lasers (femtosecond to picosecond pulses). Each TGV is 50-100µm diameter through 0.4-1.0mm of glass; a typical AI substrate panel carries 100,000-500,000 TGVs at sub-µm positional accuracy. The yield-gating reality: industry first-production-line yield is 30-50% today vs the >70-80% needed for commercial scale. Yield is the single metric that gates the whole industry's commercial readiness — track year-over-year yield improvement at the lead (Japanese) substrate maker.

Glass formulation variants, with their tradeoffs:

Type	Composition	Pros	Cons	Use
Borosilicate	Boron + silicate base	Workable, low CTE (~3-5 ppm/°C), reasonable price	Some thermal limits	Mainstream candidate
Fused silica	Pure SiO2	Lowest CTE (~0.5 ppm/°C), highest thermal	Expensive, hard to make in large panels	Premium; limited use
T-glass / specialty	Engineered low-CTE blends	Tunable properties	Proprietary recipes	Vendor-specific (Nittobo T-glass)
Q-Glass (per STF)	High-performance grade for AI substrate	Tightest tolerances	Limited supply	Vera Rubin generation

Architecture variants run all-glass-core / organic build-up (the most common Intel GlassCore reference) → glass-core + glass-build-up (long-term, not deployed) → hybrid glass+organic sandwich (transitional demonstrators). Q-Glass — flagged in STF's Kitagawa Seiki coverage as next-gen Vera Rubin material — is the single most important grade to track for 2027-2028 deployment.

Who plays. The value chain splits into a material tier, an equipment tier, and a fabrication tier. Glass material producers: Corning GLW, AGC 5201, Nippon Electric Glass 5214, Schott (private), Hoya 7741 (adjacent via photomask glass). TGV equipment (the highest-leverage bottleneck): E&R Engineering 8027 (validated TGV laser process 2024), LPKF LPKF (LPK.DE), DISCO 6146 (singulation adjacency), MKS/Coherent (laser sources), Trumpf (private), Tango Systems (private). Substrate fabricators rebuilding their process libraries for glass: Ibiden 4062, Shinko 6967, Unimicron 3037, Nan Ya PCB 8046, Samsung Electro-Mechanics 009150, AT&S ATS, Daeduck 008060, Kinsus 3189. End customers package through OSATs (Amkor, ASE, JCET, Powertech) for Intel, Nvidia, AMD, Google, Amazon, Microsoft, Meta. A Trendforce report (2026-05-11) independently named the same nine listed players the vault primer maps — LPKF, GLW, AGC, NEG, LRCX, Disco, SUSS MicroTec, ONTO, KLAC — plus Schott and EV Group (both private). Third-party validation, no new names.

The investment angle. This is a 2027-2030 industry inflection but the validated equipment, qualified material, and named customers are already publicly observable. The most under-priced single layer is TGV equipment (Layer 3): small total revenue pool (~$50-200M in 2027-2028 growing to $0.5-1.5B by 2030) but structural margin and a qualified-supplier list under five names. E&R Engineering 8027 is the only public small-cap pure-play with validated TGV process — a real option on Intel GlassCore deployment, loss-making while waiting for ramp, sized as an option not a compounder. Glass material producers are diluted inside big-cap parents (packaging glass is incremental, not transformative). Substrate fabrication has no public small-cap pure-play; Ibiden 4062 is the best proxy as the #1 ABF maker (~30% share) with the most to win or lose from the transition. The glass-core TAM is ~$0-200M today (R&D/qualification volume) growing to $2-5B by 2030 if Intel's commit holds and competitors follow. Key risk to every other subsector below: glass-core displacement reduces organic ABF substrate share at >100mm packages, which delays-but-real threatens the ABF resin, copper foil, and CZ chemistry intensity per substrate (impact lagged 3-5 years).

ABF / IC substrates

What it is. The multilayer rigid plate between the silicon die and the PCB — re-routes the die's thousands of fine-pitch I/O bumps to the PCB's coarser solder-ball pattern, while handling huge I/O count (>10,000 contacts on a flagship accelerator), massive thermal load (>1kW per package), and growing physical dimensions (90×90mm and beyond). For three decades the dominant material has been organic ABF — Ajinomoto Build-up Film — a B-stage epoxy film with controlled filler loading and a release liner, laminated with copper into multilayer organic substrates over a BT-resin / glass-cloth core. Hopper, Blackwell, Sapphire Rapids, Granite Rapids all run on ABF substrates.

The technology. A core sheet (0.4-1.0mm) provides structure; 3-5 build-up layers per side carry traces; through-vias connect top to bottom. AI accelerator substrates run 20-24 build-up layers today → 28-32+ for Vera Rubin class. The Ajinomoto chemistry is a near-monopoly: ABF is in >90% of advanced organic substrates globally and has never been credibly second-sourced. A fire at Ajinomoto's Kanagawa plant in 2020 caused a 90-day shortage — repeated today it would halt the AI substrate ramp for a quarter. The most credible challenger is Sekisui's SEKIRES low-Dk PI film at <5% share (trailing-edge use only). Current ABF GZ resin is roughly Dk=3.2 / tan-δ=0.005 at 10GHz; Vera-Rubin-era substrates need closer to Dk=3.0 / tan-δ=0.003 (the GZ-N generation).

Who plays. Substrate fabricators (5-firm oligopoly, ~$15-20B revenue pool, 25-35% GM cycle-dependent): Ibiden 4062 (#1, ~30-35% advanced share, ~40-50% of flagship Vera Rubin volume; Intel/AMD/Nvidia/AWS/Google source flagship substrates here), Shinko 6967 (#2, ~20-25%, FCBGA leader), Unimicron 3037 (~20-25%), AT&S ATS (#5 globally ~5-8%, Europe's only scaled player, AMD anchor, Kulim Malaysia ramp), Samsung Electro-Mechanics 009150 (~10-12%). Resin: Ajinomoto 2802 (>90% ABF, but ~5% of a food/healthcare conglomerate's revenue). Substrate-grade BT resin: Mitsubishi Gas Chemical 4182.

The investment angle. The fab tier is fully priced — Ibiden is up ~6.7x; the AI substrate bull case is consensus. Ibiden's R/R from here is symmetric (consensus catch-up trade); the verdict is WATCH at ¥14-14.5k or after a sell-side PT revision wave, not initiate. Customer concentration is the structural risk (Intel + Nvidia + AMD >60% of Ibiden substrate revenue). Ajinomoto's near-monopoly resin is the single most acute concentration risk in the entire AI supply chain, but it is not Pink-actionable as a pure play — ABF is too small a slice, the food business trades at staples multiples and won't re-rate, and the SOP arbitrage (worth 20-30% if you SOP-valued ABF at substrate multiples) is too well-known and too slow to unwind on retail timeframes. The substrate fabricator is where the dollar volume sits but the chemistry and material layers below it capture more gross profit per dollar of fab revenue — which is the bridge to the next subsector.

Copper-wiring / resin sub-layer

What it is. One layer below the substrate fabricator: the copper-metal + dielectric-resin interface where AI accelerator electrical signals physically live. A modern accelerator package is a 3D wiring problem — 50,000+ solder bumps at 130µm pitch fanning out over 20+ stacked copper layers to a 4,000-pin BGA, each layer a sandwich of copper trace plated into resin. The fabricator owns the process integration and the customer slot; the chemistry suppliers own the spec inside that slot. This is where the bottleneck and the mispricing live.

The technology — three consumable chemistries, each near-monopoly. (1) Premium copper foil: at fine-line RDL (2µm features, 1µm thickness) even electrodeposited foil is too thick, so you need carrier foil — thin Cu bonded to a peelable support. Mitsui Kinzoku's MicroThin owns this (>90% share). (2) ABF resin (covered above). (3) CZ microetching — MEC's franchise — solves copper-to-resin adhesion: too smooth = no adhesion (resin slides off), too rough = signal loss at high frequency. The CZ chemistry etches copper grain boundaries to ~0.1µm controlled roughness, threading the needle between mechanical interlock and signal integrity. Three first-principles physics limits set the engineering space: skin effect (at 28GHz copper skin depth is ~0.4µm, so surface roughness directly costs signal — lower roughness lowers loss but worsens adhesion), adhesion physics (below ~0.1µm Ra mechanical interlock fails and chemical bonding must do the work — MEC's next-platform AP series uses a self-assembled monolayer for no-roughening adhesion, enabling sub-2µm RDL), and dielectric tan-δ / Dk (resin loss sets insertion loss).

The metrics roadmap, Blackwell → Vera Rubin:

Metric	Today (Blackwell-class)	Next (Vera Rubin-class)	Supplier implication
Line/space (µm)	8/8 typical, 5/5 high-end	2/2 leading edge	MEC AP-series enabling; MicroThin volume rises
Build-up layers	20-24	28-32+	More CZ baths, more ABF film per substrate
Substrate area (mm²)	5,625	8,100+	Cu foil + ABF panel demand scales linearly with area
Microvia diameter (µm)	50	35-40	Laser drill capability + resin filler control
Dielectric tan-δ @ 10 GHz	0.005	0.003	Ajinomoto GZ-N or competitor displacement
Cu surface roughness Ra (µm)	0.1	0.05 or sub-roughening	MEC AP series replaces CZ at flagship tier
ABF film thickness (µm)	25-40	15-25	Ajinomoto + Mitsui MicroThin pairing
Cu foil thickness (µm, post-carrier)	3-5	1-2	MicroThin volume scales; standard ED foil de-mixes

Copper foil tiers ladder cleanly by node — as substrate node shrinks the fabricator buys more expensive Cu foil per area: Standard ED (12-35µm, commodity ~10-15% GM, Furukawa/Nippon Denkai/Iljin) → Low-profile LP (12-18µm, ~25-35% GM) → High-grade VSP/HVLP (9-18µm, ~35-45% GM, Mitsui >50% share) → MicroThin carrier foil (1.5-5µm, ~45-55% GM est, Mitsui >90% share, only product qualified at the leading edge).

Who plays. The concentrated franchises: MEC Company 4971 (CZ + AP chemistry, ¥12B revenue, 62% gross margin, ~100% PC CPU substrate adhesion / 70-80% advanced, qualified CZ-8101 into CoWoS chiplet packaging), Mitsui Kinzoku 5706 (MicroThin Cu foil monopoly hidden in a smelter — foil ~14% of a ¥729B group but ~40% of Engineered Materials segment ordinary income), Ajinomoto 2802 (ABF resin). Adjacent surface chemistry: desmear / electroless Cu / final finish from Atotech (now MKS), Uyemura 4966, Dow/Okuno (2-3 vendor oligopolies, less monopolistic). Solder resist: Taiyo Ink 4626 (~60-70% share). Catch-up threats 18-36 months behind at flagship tier: SK Nexilis (009070.KS), Iljin Materials (020150.KS), Nuode (600110.SH) — all battery-foil-distracted or China-qualification-constrained.

The investment angle. The defining structural fact: the chemistry layer (Cu foil + ABF resin + CZ adhesion) collectively earns more gross profit per dollar of substrate-fab revenue than the fab itself, at one-tenth the headline revenue and one-twentieth the market cap. It is also less cyclical — in the 2018-2020 substrate downcycle fab revenues dropped 25-35% while MEC's CZ revenue dropped <10% and Mitsui's MicroThin volume dropped ~5% (consumable per panel, not capex; spec-lock prevents switching; sticky pricing). But all three names have already moved 3-12x: Mitsui +11.8x in 12mo, Ibiden up 6.7x, MEC up 3.4x. The trade-from-here is disciplined re-entry on pullbacks, not initiation. The single mispriced option the market hasn't underwritten: MEC's AP-series next-platform extension into sub-roughening adhesion for sub-2µm RDL — at a ¥7-9k entry you get that option for free on top of the CZ franchise. Mitsui is the only name where the SOP re-rating (smelter multiple → specialty-chem multiple on the foil sub-segment) is visible but not complete. The LITE/COHR 2024 playbook (NVDA EML pre-allocation → upstream optics +955%) maps here with MEC as the LITE-equivalent and Mitsui as the COHR-equivalent — except both have already run, so it's re-entry not initiation.

CCL materials (glass cloth + resin + premium laminate)

What it is. Two layers below the AI server PCB fabricator: the woven fiberglass cloth and the resin matrix that combine with copper foil into copper-clad laminate (CCL), the raw material of every PCB. This subsector feeds both the AI server PCB and (via T-glass) the IC substrate. The thesis: the market clusters attention on named PCB fabricators, but the alpha is two layers upstream in glass cloth and resin, where the supply curve has gone vertical while consensus models still assume commodity material.

Why now — a simultaneous double squeeze. In 2025 Nittobo, the world's most important fiberglass cloth maker, told customers it was exiting the ultra-thin high-end E-glass that goes into AI server CCL, to focus on LDK and T-glass for IC substrates. This is a structural withdrawal of capacity from a layer everyone downstream depends on. E-glass thin fabric prices rose ~30% YTD as of April 2026 with another doubling priced in for 2026; Taiwan Optical Electronics forecasts a 2 million meters/month LDK2 supply gap by 2H26. Simultaneously, in mid-April 2026 SABIC — which controls ~70% of world PPO resin supply — lost 25-30% of its Saudi capacity to a natural-gas constraint. PPO is the resin in low-loss CCL. So both reinforcement (glass cloth) and matrix (PPO resin) of every AI server laminate went short at once.

The technology. AI server boards need CCL with Dk ~3.0-3.5 and Df <0.002 at 28GHz; standard FR-4 (Dk ~4.5, Df ~0.02) is unusable. The materials that hit spec — Panasonic Megtron 6/7/7N/8, Rogers RO4000, Shengyi S7460, ITEQ IT-988GSE — all use low-Dk glass cloth (LDK1, LDK2, sometimes T-glass) plus PPO/PPE resin. CCL grade and supplier are tied: M7/M7N is Panasonic-dominated with Shengyi/EMC as credible alternates; M8 is essentially Panasonic alone with Shengyi catching up. Every grade step (Megtron 6 → 7 → 7N → 8 → M9) is a multi-year share-shift event because qualification takes 12-18 months and the board must be re-tested with the new laminate.

CCL grade ladder by cost and application:

Material	Application	Dk @ 28GHz	Df @ 28GHz	Cost / sqm
FR-4	Consumer, low-end	~4.5	~0.020	1x baseline
Megtron 6	High-speed networking	~3.7	~0.005	4-5x
Megtron 7 / 7N	AI accelerator boards	~3.4	~0.003	8-10x
Megtron 8 / Tachyon 100G	Next-gen 224G SerDes	~3.0	~0.0015	12-15x
BT resin substrate	IC substrate	~3.4	~0.005	20-30x (smaller area)

Who plays. Glass cloth (top 3 ~70% share): Nittobo 3110 (tech leader, exiting E-glass for LDK/T-glass), Fulltech 1815 (30-40% E-glass / 60-70% LDK — direct Nittobo-exit beneficiary), Taiwan Glass (1802.TW), Unitika 3103. PPO resin: SABIC (~70%, parent 2010.SR), DIC, Asahi Kasei. CCL makers: Shengyi 600183 (China #1, rising in premium), Elite Material 2383 (Taiwan #1), ITEQ 6213, TUC 6274, EMC 1909, Panasonic Megtron (the de facto premium standard, but un-investable inside a ¥3T conglomerate), Mitsubishi Gas Chemical 4182, Doosan (KS:000150). Vacuum-press equipment for lamination: Kitagawa Seiki 6327 (world #1, STF hidden champion, sole supplier qualified for M9/Q-Glass tolerances). Solder mask / dry film: Taiyo Holdings 4626 (Rubin substrate 100% dry film, Zaristo carries 30-50% ASP premium, FPIM co-developed with imec for Rubin's <2µm RDL HBM4 base die).

The investment angle. Glass cloth is the highest-barrier tier in the whole PCB stack even though it has lower capex per ton than a CCL line — qualification cycles and tribal know-how, not capital, build the moat (switching a glass cloth maker takes 12-18 months because the CCL maker re-qualifies the cloth, then the PCB fab re-qualifies the CCL). The single most under-priced layer is high-end glass cloth (Layer 2): ~$8-12B revenue pool, fast-expanding margin, top-three control 70%+. Fulltech 1815 is the smallest pure-play (~$0.6B cap) — direct Nittobo-exit beneficiary, EPS NT$6-8 in 2026 / ~NT$10 in 2027 per Taiwanese sell-side, top of the follow-up list. Premium CCL (Shengyi the closest investable proxy) is the next-best alpha as glass cloth and PPO tightness flows into laminate margin. The Goldman Sachs January 2026 TAM revision frames the demand: AI CCL TAM $18.3B in 2027 (up from prior $8.0B, ~178% CAGR 2025-2027) vs AI PCB TAM $26.6B (~140% CAGR) — CCL grows faster than finished PCB precisely because yield erodes (24-28 layers / 4+N+4 in 2025 → 40+ layers / 6+N+6 in 2027 drops industry yield ~73% → ~62%), so more raw CCL is scrapped per finished panel. The repeating pattern: the named PCB fabs are priced; the second-derivative material tier is not.

Silicon capacitors

What it is. A chip-form capacitor fabricated on a silicon wafer using semiconductor lithography and etching — trenches etched into silicon to maximize surface area, coated with high-permittivity dielectric (Al2O3 or HfO2 via atomic layer deposition), then metallized. Behaves more like a tiny silicon die than a traditional ceramic capacitor. It does not replace MLCC in volume — it complements MLCC in three specific places: ultra-high frequency, ultra-thin packaging, and embedded-in-substrate.

The technology — how it differs from MLCC. Silicon caps win on ultra-thin form factor (80-100µm vs 200-1,000 for MLCC), ultra-low ESL (<0.1 nH vs 0.3-1 nH), and effective frequency response above 1 GHz (vs ~100 MHz for MLCC). They lose on cost ($0.10-1 each vs $0.001-0.10 for MLCC) and maximum capacitance (mostly <100 nF vs up to 220 µF in a 1206-size MLCC).

Why it's the new bottleneck. AI accelerator packaging is moving to 2.5D technologies (Intel EMIB, TSMC CoWoS-S, Samsung I-Cube) that integrate multiple dies on a common substrate. Each die needs power delivery integrated as close to the silicon as the package allows — MLCC on the PCB is too far, MLCC on the package top is too far for the highest-frequency rails. Silicon caps solve this by sitting embedded in the bridge, interposer, or ABF substrate. The structural unlock, per Jukan: silicon caps failed to grow until now because TSMC, holding overwhelming AI-packaging substrate share, sourced silicon caps in-house, making it effectively impossible for outside suppliers to break into the value chain. Intel's EMIB changes that — Intel cannot make its own silicon caps and must source externally, opening the door to Murata and SEMCO. Three design wins drive the demand step-change: Google v8e TPU (2H 2027 launch) on EMIB with embedded silicon caps, Intel EMIB scale-up from 2027 (covers Microsoft Maia, Amazon Trainium, NVIDIA networking, Intel's own products), and Amazon Trainium/Inferentia pulling silicon-cap content via Intel.

Who plays. Four qualified suppliers: Murata 6981 (acquired IPDiA 2016, production in Caen France; close Ibiden relationship positions it for EMIB), Samsung Electro-Mechanics 009150 (in-house), AP Memory 6531 (Taiwanese, TSMC fab partnership), and TSMC 2330 itself (Integrated Passive Devices on advanced nodes, sold as part of the foundry package, not separately reported). Murata and TSMC have internal demand from their own packaging, leaving SEMCO and AP Memory as the merchant suppliers with the most addressable external order book. Zephyr flagged silicon caps experiencing supply tightness "likely to pop off like MLCC players," with Murata, SEMCO, AP Memory the highest-exposure names.

The investment angle. SEMCO's edge is not "silicon cap supplier among several" — it is "the only company in the world that operates both a silicon capacitor business and a substrate business," giving it a turnkey substrate + silicon cap bundle for Intel EMIB that maximizes bargaining power (the substrate is the highest-value EMIB BoM component). Citi: SEMCO silicon-cap revenue W609bn FY27E / W905bn FY28E, anchored by a W1.6T two-year supply order (Jan 2027-Dec 2028) from a "major global company" (likely Google v8e); already supplying Marvell. But the valuation math doesn't justify the price: at SEMCO market cap W140T, a sum-of-segments framework (MLCC + FC-BGA + silicon cap + camera modules + net cash) lands at gross SOTP of W60-63T (~KRW 825-870K) on moderate assumptions; the aggressive bull case (silicon cap to W2-3T by FY29-30, FC-BGA at full TSMC multiples) reaches ~KRW 1.25M — still 32% below the KRW 1.85M market price. The turnkey premium bumps bull-case fair value to maybe KRW 1.4-1.5M, still 20-25% below. AP Memory 6531: core business is PSRAM and high-speed SRAM, but silicon-cap exposure is real and disclosed — two product lines (discrete S-SiCap IPD, Gen3 in production / Gen4 ramping 2026; and silicon-capacitor interposer IPC, four-reticle mass production from end-Q3 2025), Intel EMIB first-qualified-supplier May 21 2026 with Q2 2026 shipment start, CoWoS-S/L adjacency at TSMC additive. Silicon cap is est. 15-25% of FY2025 NT$5.67B revenue (segment split not officially disclosed — the #1 valuation risk). The stock at NT$1,080 is +365% in 13 months, 42x forward PE, +39% above MS's raised PT of NT$777: verdict PASS at NT$1,080 / WATCH NT$650-800 / BUY NT$400-550. The pattern repeats — strong structural thesis, stretched price.

SiP / OSAT / RF modules / silicon photonics

What it is. The assembly subsector — where heterogeneous components are physically integrated into a single functional module. Historically integration happened on a PCB; that stopped scaling for phones around 2010 (board too big, lossy, expensive) and is stopping now for data centers (electrical interconnect at 51.2T+ switch bandwidths burns too much power). Two responses: miniaturize the PCB onto a stamp-sized substrate (SiP, system-in-package) or eliminate electrical interconnect by co-packaging optics next to the ASIC (CPO, co-packaged optics). OSATs (outsourced semiconductor assembly and test) are the contract manufacturers of this integration. The OSAT layer has three sub-markets with margins rising left to right: commodity OSAT (wirebond/leadframe/FCBGA, ~12% GM) → specialty SiP / RF module assembly (~15-18% GM) → optical / silicon photonics assembly (20-30%+ GM).

SiP — System-in-Package. A laminate or silicon substrate ~5×5mm to 20×20mm carrying multiple dies of different technologies flip-chipped or wire-bonded together with SMD passives, encapsulated in epoxy molding compound, presenting as a single "chip." Canonical products: RF front-end modules (GaAs PA + silicon controller + filters, BOM $3-8), Wi-Fi FEMs (BOM $1-4), wearable SiP (Apple Watch S-series, AirPods — SoC + memory + PMIC + BT + sensors), sensor modules. SiP wins on density (3-5x vs PCB), speed (shorter traces), cost at volume for heterogeneous workloads (you can't fab a PA and a CMOS controller on the same wafer), and time-to-market; it pays in thermal management, yield compounding, and test complexity. Winners: USI (601231.SH, ASE subsidiary — #1 merchant SiP house globally, ~US$7B revenue, ~17% EBITDA, Apple Watch/AirPods), ASE 3711 (does SiP directly and via USI; world #1 OSAT overall), Amkor AMKR (distant third, strong in auto SiP), Murata 6981 (MetroCirc SiP substrate), ShunSin 6451 (niche RF-SiP/MEMS for Chinese Android and Foxconn-adjacent sockets, sub-scale ~US$230M).

RF front-end modules. RF content per smartphone rose from ~US$15 BOM (4G) to ~US$35-40 (5G + Wi-Fi 7 + UWB + satellite). TAM US$29B in 2025 → US$54B by 2030 (13% CAGR) — driven by content growth per device, not unit growth (handset units flat). IDM side: Skyworks SWKS, Qorvo QRVO (announced a US$22B merger in 2025 consolidating the RF-FEM IDM landscape), Broadcom AVGO (FBAR filters), Qualcomm-TDK RF360 JV, Murata 6981. IDMs do most packaging in-house, so merchant OSATs capture only secondary sockets and overflow. Apple's in-sourcing wave (2025 N1 chip, iPhone 17 Pro — first in-house Wi-Fi 7 + BT silicon) hurts Broadcom; packaging flow likely stays through Foxconn (neutral-to-positive for ShunSin).

OSAT industry structure. Top 10 OSATs, US$41.6B global revenue (2024, +3% YoY per TrendForce):

#	Company	Ticker	2024 Rev (US$B)	Share
1	ASE Technology	3711 / ASX	18.5	44.6%
2	Amkor	AMKR	6.3	15.2%
3	JCET	600584.SS	5.0	12.0%
4	Powertech	6239	~2.9	7.0%
5	TFME (Tongfu)	002185.SZ	~2.3	5.5%
6	Huatian	(verify code)	~2.0	4.8%
7	WiseRoad	private	~1.5	3.7%
8	Hana Micron	067310.KS	~0.9	2.2%
9	KYEC (King Yuan)	2449	~0.9	2.2%
10	ChipMOS	IMOS	0.7	1.7%

Segment specializations: memory packaging (Powertech, Hana Micron, captive Samsung/SK Hynix), test (KYEC pure-play, AI/HBM-test re-rating — HBM test time 3x DRAM), SiP/modules (USI, ShunSin, Nepes, Amkor auto), advanced pkg 2.5D/3D/FOWLP/CoWoS-class (TSMC insourced + ASE + Amkor + Japanese interposer specialists Shinko/NTT AT), optical/photonics (Fabrinet + specialty Asian + ShunSin CPO). OSATs run capex/revenue ~10-15% normal / 20%+ cycle-up; a modern advanced-packaging line costs US$100-300M; hyperscaler qualification takes 12-18 months with extremely high mid-program switching costs. TSMC CoWoS booked through 2026; ASE's CoWoP (CoWoS-on-PCB) and CoWoS capacity tripling (~20-25k wafers/mo by end-2025) is the biggest OSAT-level capex event.

Silicon photonics & CPO — the inflection. AI switch bandwidth scales 25.6T → 51.2T (2024-25) → 102.4T (2025-26) → 204.8T (2027-28). At 51.2T+, electrical interconnect off the switch ASIC becomes unacceptable — the wire drinks too much energy moving bits 30cm. The physics: electrons are cheap to switch but expensive to move; photons are expensive to generate but essentially free to move. Silicon-photonics transceivers use CMOS wafers patterned with waveguides and Mach-Zehnder modulators at 100+ Gbps/lane, with external InP lasers coupled in (silicon is a poor light emitter); per-bit energy ~5 pJ/bit today, target <1 pJ/bit by 2028. The hard parts: laser attach (flip-chip InP onto SiPh substrate at sub-micron alignment, yield-limiting), FAU (Fiber Array Unit) attach (the single highest-skill step — 200nm misalignment costs 1 dB insertion loss), thermal control (ring-resonator modulators drift 80 pm/°C), hermetic seal. Who does it: Fabrinet FN (biggest contract optical assembly house, ~US$3B revenue, mature hyperscaler-qualified FAU-attach, ~12% GM), Intel's Ireland photonics op, Coherent COHR / Lumentum LITE (InP laser and finished-module IDMs), Innolight 300308 / Eoptolink 300502 (Chinese pluggable transceiver pure-plays, US$1-3B revenue, 30%+ GM), ShunSin 6451 (emerging FAU-attach in Nvidia/Broadcom CPO supply chain, ~US$145M optical segment). CPO economics: a 51.2T module integrates ~64× 800G channels, finished ASP $3,000-5,000, assembly margin 20-35% GM at scale. The adoption risk: CPO has been 2 years away for 5 years — pluggable optics at 1.6T narrow the power advantage, hyperscalers have paused and restarted programs, the risk is the TAM slips right again. TSMC's COUPE (Compact Universal Photonic Engine) is the insourced-at-TSMC SiPh play; if TSMC captures CPO packaging at scale the merchant opportunity shrinks, but CoWoS capacity constraint means first-generation spillover to merchant OSATs is probable.

The investment angle. Margin uplift rank order 2026-28: CPO > advanced pkg (CoWoS class) > HBM test > SiP > commodity OSAT. Trading multiples (April 2026) show two EV/Revenue outliers: KYEC 2449 (10.1× EV/Rev, AI-test pure-play with 46% EBITDA margin — paid for the narrative and the prints justify it) and ShunSin 6451 (7.5× EV/Rev, 68.8× EV/EBITDA on 11% EBITDA — priced for CPO/SiPh optionality, the speculative tier where the multiple is not yet justified by current prints). Investment frames: cycle play ASE 3711 / Amkor AMKR (liquid, diversified); HBM/AI-test pure-play KYEC 2449 (best-margin OSAT, already re-rated); SiP pure-play USI (601231.SH); optical packaging Fabrinet FN / Coherent COHR / Lumentum LITE; Chinese transceiver pure-plays Innolight 300308 / Eoptolink 300502; Foxconn-channel specialty ShunSin 6451 (AI-adjacent optionality, priced for execution). The three-derivative test for any name: is the sub-segment up-cycle, is the mix shifting toward higher-margin, is the company gaining share within its sub-segment — multibaggers sit where all three arrows point up.

Cross-subsector synthesis

The subsectors interlock vertically. Glass-core is the long-dated disruptor that threatens the ABF substrate, copper-foil, and CZ-chemistry intensity per package from 2030. ABF substrate is the priced fabricator tier; the copper-wiring/resin sub-layer beneath it is where the concentrated consumable margin lives (and where the market has only partly re-rated). CCL materials feed both the AI server PCB and the IC substrate, with glass cloth the single highest-barrier, least-priced layer. Silicon capacitors are the newest bottleneck, unlocked by Intel EMIB breaking TSMC's in-house lock. SiP/OSAT/photonics is the assembly subsector where the heterogeneous integration physically happens. The recurring investment lesson across all six: the named beneficiary is well-priced, the alpha is one-to-two layers upstream in a single-vendor consumable or material tier, and as of mid-2026 most of those upstream names (Mitsui, MEC, Fulltech-watch, E&R, AP Memory) have either already run hard or carry specific-execution / disclosure risk — making disciplined re-entry on pullbacks the operative posture rather than initiation at current prices.

Value chain

Advanced packaging is not one value chain — it is four interlocking ones stacked vertically inside an AI accelerator package, plus a fifth (silicon capacitors) that threads through the substrate. From the silicon die downward: the IC substrate (organic ABF today, glass-core tomorrow), the substrate sub-layer chemistry (the copper-and-resin interface inside the substrate), the PCB stack (the board the substrate solders onto), and the OSAT / SiP / photonics integration layer (where heterogeneous dies are physically assembled). Each has its own raw-material tier, its own bottleneck tier, its own fabricator oligopoly, and its own margin geography. The recurring structural fact across all of them: the dollar volume sits downstream at the fabricators, but the pricing power sits two layers upstream in concentrated specialty materials and equipment. The market prices the fabricators; the alpha is in the bottleneck tiers it hasn't.

The AI server PCB chain — seven layers, alpha two layers upstream

The PCB is the largest single non-silicon line item in an NVIDIA NVL72 rack. A single GB200 rack consumes more advanced PCB area than a smartphone factory's annual output. The chain runs:

LAYER 1 — Raw materials
  Glass yarn:        Nittobo, Taiwan Glass, Owens Corning, AGY, Unitika
  Resin (PPO/PPE):   SABIC (~70% global), DIC, Asahi Kasei
  Resin (BT):        Mitsubishi Gas Chemical, DIC
  Copper:            commodity
LAYER 2 — Glass cloth / Copper foil (★ BOTTLENECK TIER)
  Glass cloth:       Nittobo (3110.T), Fulltech (1815.TW), Taiwan Glass, Unitika (3103.T)
  Copper foil:       Mitsui Mining & Smelting (5706.T), Furukawa (5801.T), Iljin Materials
LAYER 3 — CCL / Prepreg (★ BOTTLENECK TIER)
  Premium CCL:       Panasonic (Megtron), Shengyi (600183.SH), Mitsubishi Gas Chemical
  Standard CCL:      Elite Material (2383.TW), ITEQ (6213.TW), TUC, EMC (1909.TW), Doosan
LAYER 4 — PCB fabricators (the "named" winners)
  AI server PCB:     Victory Giant (002476.SZ/2476.HK), Shennan (002916.SZ), Suntak,
                     Aoshikang, Tripod (3044.TW), Unimicron (3037.TW), Compeq (2313.TW),
                     GCE (2368.TW), Nan Ya PCB (8046.TW), Ibiden (4062.T)
LAYER 5 — Drilling / Equipment / Consumables
  Drill bits:        Union Tool (6278.T), Tungaloy, Kyocera Precision
  Drill machines:    Mitsubishi Electric (CO2), Via Mechanics (UV), Schmoll, Posalux
  Vacuum press:      Kitagawa Seiki (6327.T)
  Test/AOI:          Camtek (CAMT), Orbotech (NDSN)
LAYER 6 — System integrators / ODM
  Foxconn (2317.TW), Quanta (2382.TW), Wiwynn (6669.TW), Inventec, Supermicro (SMCI)
LAYER 7 — End customers
  NVIDIA, Google, Amazon, Microsoft, Meta, Tesla

Where the profit pools sit (2026E, AI server PCB chain):

Layer	Revenue pool '26E	Gross margin range	Concentration	Where the alpha lives
1 — Raw materials	$5-8B	25-35%	Medium (SABIC dominant in PPO)	SABIC outage = priced
2 — Glass cloth / Cu foil	$8-12B	30-50%	High — top 3 glass cloth ~70%	Yes — Nittobo/Fulltech bottleneck
3 — CCL	$25-35B	25-35% premium / 15-20% standard	Medium-high	Yes — premium CCL squeeze
4 — PCB fabricators	$80-110B	25-40% advanced / 12-18% commodity	Medium	Partial — share-shift play
5 — Equipment / consumables	$5-8B	35-45%	High (Union Tool, Mitsubishi)	Already priced
6 — ODM	$300-400B	4-8%	High (Foxconn dominant)	Low margin, no pricing power
7 — End customer	n/a	n/a	n/a	Where the demand comes from

The single most under-priced layer is Layer 2 — high-end glass cloth: small revenue pool but margin expanding fast and top three control 70%+. The dollar volume sits at Layer 4 (the named fabs), but the market has already priced that AI bull case — Victory Giant, Shennan, Tripod have all run hard; they remain investable as a tactical share-shift trade, not a pricing-power trade. The ODM layer (Layer 6) is the largest revenue pool by far ($300-400B) but carries 4-8% gross margins and no pricing power — Foxconn dominant, a pure throughput business.

The bottleneck mechanism is a deliberate supply withdrawal. Nittobo, the world's most important fiberglass cloth maker, is exiting ultra-thin high-end E-glass to focus on LDK and T-glass for substrates. Downstream — Shengyi, Panasonic, ITEQ, Elite Material, Victory Giant, Unimicron, Ibiden — all depend on that E-glass. As of April 2026, E-glass thin-fabric prices were up ~30% YTD with the market pricing another doubling in 2026; Taiwan Optical Electronics forecast a 2 million meters/month LDK2 supply gap by 2H26. Simultaneously SABIC, controlling ~70% of world PPO resin, lost 25-30% of its Saudi capacity to a gas constraint. PPO is the resin in low-loss CCL. A simultaneous shortage in both reinforcement (glass cloth) and matrix (PPO resin) of the laminate in every AI server board.

PCB BOM economics and yield-driven CCL leverage

The unit economics drive the entire race up the value chain. The illustrative per-board model:

• Smartphone board: 8 layers, 100% yield baseline, $5 ASP, $1.50 cost → 70% gross margin
• AI server motherboard: 30 layers, 60% effective yield, $1,200 ASP, $300 marginal cost → ~75% gross margin for boards that ship, plus ~40% inventory write-off on scrap

The AI server board generates ~5-7x the gross profit per panel-equivalent of a smartphone board even after yield loss, because ASP scales faster than cost. This is why every Asian PCB fab is racing to qualify on AI programs.

The non-obvious wrinkle in the TAM math is yield erosion driving CCL TAM faster than PCB TAM. Per Goldman Sachs (Jan 2026, via STF Research), AI PCB TAM hits $26.6B in 2027 (up from prior $17.4B; ~140% CAGR 2025-27) while AI CCL TAM hits $18.3B in 2027 (up from $8.0B; ~178% CAGR). CCL grows faster because as layer counts move 24-28 (2025) → 40+ (2027) and HDI build-up moves 4+N+4 → 6+N+6, industry yield falls from ~73% to ~62% — lower yield means more raw CCL scrapped per finished panel. The Vera Rubin (VR200/VR300) content step-up: midplane content per GPU rises to ~$171-256 (107%/57% jump vs GB300 NVL72) from 2H26; backplane content per GPU rises to ~$781-1,563 (5x/4.5x jump vs GB300) from 2H27.

Per-segment board economics: OAM/UBB baseboards (22-30 layers, anylayer HDI, Megtron 7/7N, ASP $2,000-5,000); NVSwitch/switch trays (30-50+ layers, Megtron 8, lowest-loss requirement of any board, ASP $5,000-15,000); compute/CPU baseboards (16-22 layers, Megtron 6, ASP $500-1,500); power converter PCBs (8-16 layers, heavy 3-6oz copper, ASP $200-500); IC substrates (4-2-4 to 8-2-8 build-up, ASP $50-300); optical/CPO PCB (12-20 layers, Megtron 7/7N).

CCL material grades — the choke point ladder

Material grade and supplier are tied, and each grade step is a multi-year share-shift event because qualification takes 12-18 months:

Material	Application	Dk @ 28GHz	Df @ 28GHz	Cost / sqm
FR-4	Consumer, low-end	~4.5	~0.020	1x baseline
Megtron 6	High-speed networking	~3.7	~0.005	4-5x
Megtron 7 / 7N	AI accelerator boards	~3.4	~0.003	8-10x
Megtron 8 / Tachyon 100G	Next-gen 224G SerDes	~3.0	~0.0015	12-15x
BT resin substrate	IC substrate	~3.4	~0.005	20-30x (smaller area)
ABF film	High-end IC substrate	n/a (film)	n/a	premium

M7/M7N is Panasonic-dominated with Shengyi and EMC as credible alternates; M8 is essentially Panasonic alone with Shengyi catching up. Panasonic's Megtron is the single most important premium CCL brand but is not directly investable (¥3T conglomerate; Megtron is a small high-margin slice — analytical anchor only). The closest investable premium-CCL proxy is Shengyi (600183.SH).

Barriers, switching costs, and why barrier height ≠ capital intensity

Layer	Capital intensity	Tech intensity	Qualification	Total barrier
Glass cloth	High	High (decades of know-how)	12-18 months	Very high
CCL (premium)	High	Very high (resin formulation)	12-18 months	Very high
CCL (standard)	High	Medium	6-12 months	High
PCB fab (advanced)	Very high	Very high (yield know-how)	12-24 months	Very high
PCB fab (commodity)	Medium-high	Medium	6 months	Medium
Drill consumables	Medium	High (process IP)	6-12 months	High
Drill machines	High	High	24 months	High
ODM	High	Low-medium	n/a	Medium

The non-obvious takeaway: barrier height does not map to capital intensity. Glass cloth has lower capex per ton than a CCL line, but qualification cycles and tribal know-how make it the highest-barrier tier — which is precisely what makes it a structural pricing-power layer. The switching-cost chain compounds: swap a glass cloth maker (12-18mo) → the CCL maker must re-qualify the cloth → the PCB fab must re-qualify the CCL (6-12mo) → the end customer must re-test the board. Switching a PCB fab on an AI accelerator board takes 12-24 months. These are real, measurable, multi-quarter lock-ins, and each one is what gives each layer pricing power once a customer is in.

PCB chain bottleneck ranking

Layer	Smallest pure-play	Mkt cap	Concentration	Bypassable?	Market priced-in?
Glass cloth (LDK/E-thin)	Fulltech (1815.TW)	$0.6B	High (Nittobo+Fulltech+Taiwan Glass ~70%)	No (12-18mo qual)	Under-priced
Glass cloth (T-glass)	Nittobo (3110.T)	$3.5B	Very high (Nittobo dominant)	No	Partly priced
PPO resin	SABIC (2010.SR)	n/a	Very high (SABIC ~70%)	No	Partly priced (April outage)
Premium CCL	Panasonic (6752.T)	parent $30B+	High (Pana+Shengyi+MGC)	Partial	Partly priced
Standard CCL	Elite (2383.TW), ITEQ (6213.TW)	$10B / $4B	Medium	Partial	Priced
Anylayer HDI fab	Tripod (3044.TW), Compeq (2313.TW)	$8B / $3B	Medium-high (top 5 ~70%)	No (24mo qual)	Mostly priced
AI server PCB (HLC)	Victory Giant (002476.SZ)	~$28B	Medium (top 5 ~60%)	Partial	Priced post-rerate
Drill bits	Union Tool (6278.T)	$1.9B	High (top 3 ~60%)	No	Priced (re-rated 5x)
ODM	Foxconn / Quanta	$90B / $30B	High	No	Priced

Ranked top bottlenecks: (1) glass cloth LDK/ultra-thin E-glass — Fulltech smallest pure-play, structural Nittobo exit, projected 2H26 supply gap, <$1B cap, highest alpha conviction; (2) vacuum-press equipment — 6327 Kitagawa Seiki, sole qualified supplier for M9/Q-Glass tolerances, Q1 FY2026 orders at 10-yr high (¥5.4B), GM 27.2%→31.9% YoY, PCB share of backlog 68%→85%; (3) solder mask dry film + FPIM — 4626 Taiyo Holdings, Rubin = 100% dry film (Zaristo carries 30-50% ASP premium vs liquid ink), FPIM a Taiyo+imec monopoly on Rubin's HBM4 RDL; (4) PPO resin; (5) premium CCL (M7N/M8/M9). Anylayer HDI — where the real fab moat sits — fewer than ten fabs worldwide can deliver at AI server volume and yield (Victory Giant, Unimicron, Tripod, Ibiden, Compeq, AT&S).

The supply-side cycle asymmetry: the chain is at mid-2nd inning of a 2-3 year up-cycle in the materials tier; 4th-5th inning in the named-fabricator tier. Materials capacity comes online slower (12-24 month lag) so tightness lasts longer; PCB fab capacity comes online faster (12-18 months) so named-fabricator pricing power wears off earlier.

The substrate sub-layer — copper foil, resin, and adhesion chemistry

Drop one layer below the substrate fabricator, to the copper-metal-plus-dielectric-resin interface where AI accelerator signals physically live. A modern AI accelerator package fans 50,000+ GPU solder bumps at 130μm pitch out through 20+ stacked copper-interconnect layers to a ~4,000-pin BGA. Each layer is copper trace plated into resin. Three near-monopoly chemistries gate this:

RAW MATERIALS         CHEMISTRY               CONSUMABLES          SUBSTRATE FAB       END CUSTOMER
Cu cathode ─► ED Cu foil ─┐
              ┌─► HVLP / MicroThin Cu foil ──┐
              │   (Mitsui Kinzoku >90%)       │
amino acid ───├─► ABF resin ──────────────────┤
chemistry     │   (Ajinomoto >90%)            │
              ├─► CZ microetchant ────────────┼─► ABF substrate fab ─► AI GPU/CPU
specialty     │   (MEC >70% adv.)             │   (Ibiden #1, Shinko    (Nvidia, AMD,
chemistry     ├─► Desmear / EL Cu ────────────┤    #2, Unimicron #3,     Intel, AWS,
              └─► Solder resist (PSR) ─────────┘    AT&S #4, Kinsus #5)   Google)
                  (Taiyo Ink 4626)

The build-up flow, sub-layer by sub-layer: core build (BT laminate) → drill+plate → pattern+etch → CZ microetch (MEC) → ABF lamination (Ajinomoto) → laser drill microvia → desmear (permanganate; Atotech/Dow) → electroless Cu seed → pattern plate to ~15μm → strip+etch → repeat 4-10 for each of 20+ build-up layers → solder resist (Taiyo Ink) → ENIG finish (Atotech/Uyemura). The yield-killing steps are CZ microetch (adhesion failure → delamination), laser drill (via reliability), and pattern plate (impedance variation) — each gated by a consumable chemistry sold by a near-monopoly.

The value-capture split is the whole point. The substrate fabricator (Ibiden, Shinko, Unimicron, AT&S) owns the process integration, the customer relationship, and the qualification slot. The chemistry suppliers own the spec inside that slot:

Layer	Revenue pool (global)	Gross margin	Players	Concentration	Captures the AI cycle?
Cu cathode / smelting	$200B+	5-10%	Glencore, Sumitomo Metal, Mitsui K.	Fragmented	No — commodity wrapper
Premium Cu foil (HVLP/MicroThin)	~$2-3B	35-55%	Mitsui K. >90% top tier	Single-vendor	Yes — 12% hike Apr 2026, no pushback
ABF resin	~$1.5-2B	~30-35%	Ajinomoto >90%	Single-vendor	Yes — but at staples multiple in conglomerate
CZ + adhesion chemistry	~$0.5-1B	60%+	MEC ~70-100% by sub-tier	Single-vendor	Yes — but rate-limited by capex
Desmear / EL Cu / surface finish	~$1-1.5B	25-35%	Atotech, Uyemura (2-3 oligopoly)	Moderate	Partial
Solder resist	~$0.8-1B	30-40%	Taiyo Ink ~60-70%	Single-vendor	Partial
ABF substrate fab	~$15-20B	25-35% (cyclical)	Ibiden, Shinko, Unimicron, AT&S, SEMCO	5-firm oligopoly	Yes — but ALL visible to market

The investable observation: the chemistry layer (Cu foil + ABF resin + CZ adhesion) collectively earns more gross profit per dollar of substrate-fab revenue than the fab itself, at one-tenth the headline revenue and one-twentieth the market cap. The market priced the fab layer (Ibiden +6.7x), is only just pricing the foil layer (5706 Mitsui +11.8x in 12mo, mostly because the smelter wrapper hid the franchise), and has not priced the adhesion-chemistry tier (4971 MEC up "only" 3.4x while owning the highest GM in the chain).

The copper-foil tier ladder maps directly to substrate node — as the node shrinks, the fab buys more expensive Cu foil per unit area:

Tier	Thickness (final)	Use case	Suppliers	Margin
Standard ED	12-35μm	Standard PCB, low-end CCL	Furukawa, Nippon Denkai, Iljin	Low (~10-15% GM)
Low-profile (LP)	12-18μm	High-speed CCL, server PCB	Mitsui Kinzoku, Furukawa, Iljin	Mid (~25-35% GM)
High-grade VSP / HVLP	9-18μm	AI server CCL, low-loss substrate	Mitsui Kinzoku (>50%), Furukawa, Iljin	High (~35-45% GM)
MicroThin carrier foil	1.5-5μm	ABF substrate fine-line RDL	Mitsui Kinzoku (>90%)	Very high (~45-55% GM est.)

MicroThin is the only product qualified at the leading edge — full stop. Korean (SK Nexilis, Iljin) and Chinese (Nuode) H-VLP3 makers are 18-36 months behind on qualification at AI substrate tier; the threat is real at the second (HVLP) tier, not at MicroThin, where Mitsui has runway through 2027-2028. On the resin side, ABF is a >90% Ajinomoto near-monopoly with Sekisui SEKIRES (PI film) the most credible challenger at <5% share. On adhesion, MEC stands alone on Cu microetch — CZ-series ~100% PC CPU substrate, ~70-80% advanced substrate; the moat is spec lock (every fab has CZ-8101 in its 8-D qualification doc; swapping triggers a full re-qual), not patent IP, which is why MEC sustains 62% gross margins on a ~¥12B base and is capacity-constrained, not demand-constrained.

Substrate sub-layer bottleneck ranking and cyclicality split

Layer	Smallest pure-play	MC	Concentration	Bypassable?	Market priced?
MicroThin Cu foil	Mitsui Kinzoku (foil ~14% of group)	~$1.5-2B implied	>90%	Partial (18-36mo qual)	Partial — re-rating in progress
CZ adhesion chemistry	MEC 4971	$1.3B	~100% PC, ~70% advanced	No (spec lock)	Partial — quality priced, capacity-ceiling not
ABF resin	Ajinomoto (too large)	n/a	>90%	No (recipe lock)	Under-priced (SOP) but un-isolable
Desmear / EL Cu	Uyemura 4966/4966	4966	~$800M	2-3 oligopoly	Partial
Solder resist	Taiyo Ink 4626	~$2B	~60-70%	No (spec lock)	Priced
ABF substrate fab	Ibiden, Shinko, Unimicron	$5-30B each	5-firm oligopoly	No (qualification)	Fully priced

The defining structural feature: the sub-layer is cyclical at the fab tier, secular at the chemistry tier. Fabricators get whipsawed by end-market PCB cycles; chemistry suppliers do not, because (1) chemistry is consumed per panel processed, not capex-purchased — volume tracks utilization, not fab capex; (2) spec lock prevents switching even in downcycles (re-qual cost > savings); (3) pricing is sticky on the way down. In the 2018-2020 substrate downcycle, fab revenues dropped 25-35% while MEC's CZ revenue dropped <10% and Mitsui's MicroThin volume dropped ~5%. Chemistry suppliers deserve a multiple premium to fabricators within the same sub-stack. The single most acute structural risk in the entire AI supply chain is the Ajinomoto single-vendor resin position — a Kanagawa-style production disruption (a 2020 fire caused a 90-day shortage) would halt the chain for a quarter.

The glass-core substrate chain — the same map, earlier and reshuffled

Glass core is the proposed 2027-2030 replacement for organic ABF as the substrate core: a panel of ultra-flat glass replaces the organic core, with through-glass vias (TGV) laser-drilled and metallized. It fixes organic substrate's three simultaneous limits at large package area (Hopper 3,025mm² → Blackwell B200 5,625mm² → Vera Rubin 8,100mm²): CTE match to silicon (~3 ppm/°C vs organic 12-14), dimensional stability, and dielectric loss at 224G SerDes. The chain:

LAYER 1 — Glass material:  Corning (GLW), AGC (5201.T), NEG (5214.T), Schott (private),
                           Hoya (7741.T, adjacent photomask glass)
LAYER 2 — Panel + surface prep:  Asian/European specialty firms; DNS Screen, TEL, AMAT
LAYER 3 — TGV equipment + laser drilling (★ HIGHEST-LEVERAGE BOTTLENECK):
          LPKF (LPK.DE), E&R Engineering (8027.TWO), DISCO (6146.T, singulation),
          MKS/Coherent (laser sources), Trumpf (private), Tango Systems (private)
LAYER 4 — Via metallization + build-up:  AMAT, Lam Research (LRCX), TEL (8035.T)
LAYER 5 — Substrate fabrication (★ PROCESS KNOW-HOW LAYER):
          Ibiden (4062.T), Shinko (6967.T), Unimicron (3037.TW), Nan Ya PCB,
          Samsung Electro-Mechanics (009150.KS), Daeduck, AT&S (ATS.VI), Kinsus, Simmtech
LAYER 6 — End customers:  Intel, Nvidia, AMD, Google, Amazon, Microsoft, Meta
          (packaging through Amkor, ASE, JCET, Powertech)

Profit pools (2027E, substrate-only est.):

Layer	Revenue pool '27E	Margin profile	Concentration	Investability
1 — Glass material	$0.5-1B	High (specialty glass 30-50% GM)	Very high (Corning/AGC/NEG/Schott)	Diluted in big-caps
2 — Surface prep	small	Medium	Medium	Low — incidental capex
3 — TGV equipment	$0.5-1.5B	High (capital equip, 30-45% GM)	High — <5 qualified suppliers	★ Best alpha layer (small caps)
4 — Build-up equipment	shared w/ semicap	Medium	Medium-high	Diluted
5 — Substrate fabrication	$5-10B by 2030	Medium-high (25-40% GM if yield holds)	Medium (top 5 = 70%+)	Direct exposure
6 — End customer	n/a	n/a	High	Diluted

The most under-priced single layer is Layer 3 — TGV equipment: small revenue pool, structural margin, short qualified-supplier list. 8027 E&R Engineering is the only public small-cap pure-play with validated TGV process (qualified 2024 by a Japanese substrate maker after 5-year co-development with a North American IDM; the customer is the Japanese substrate maker, not Intel directly). The Layer 1 glass producers (Corning, AGC, NEG, Schott) have so much adjacent revenue — display glass, optical fiber, photomask blanks, automotive glass — that packaging glass is incremental, not transformative.

The critical value-chain dynamic: incumbents do not automatically win the next generation. Glass-core manufacturing differs from organic at almost every step — laser-drill-only via formation (no mechanical option), newer high-aspect-ratio via plating, fresh build-up process development, immature laser-score-and-break singulation, an equipment ecosystem concentrating to <10 qualified suppliers globally. The substrate makers (Ibiden, Shinko, Unimicron, AT&S, Samsung E-M) must rebuild their process libraries for glass core — they cannot port ABF know-how 1:1. That is what creates the share-shift opportunity. First-production-line yield sits at 30-50% today versus the 80%+ needed for commercial scale; yield is the gating metric, and year-over-year yield improvement at the Japanese substrate maker is the leading indicator for the whole industry's commercial readiness. Switching costs once a maker qualifies on glass core for a specific customer are extreme: a 12-24 month qualification creates structural lock-in for early movers.

Glass-core's bottleneck ranking: (1) TGV equipment — 8027 E&R, only validated public small-cap pure-play, real-option exposure to Intel GlassCore; (2) specialty glass — NEG/Hoya/AGC, high concentration but parent revenue dilutes (5214, 7741, 5201); (3) glass-substrate fabrication — no public pure-play, best proxy is Ibiden as the maker most exposed to either winning or losing the transition. Trendforce's May 2026 named-player list (LPKF, Corning, AGC, NEG, Lam Research, Disco, SUSS MicroTec, ONTO, KLAC) maps the same value chain as the primer — third-party validation, no new names.

Glass-material business-model divergence (Layer 1)

Within the Layer-1 glass triad, business quality diverges sharply, which matters because it determines how much of the glass-substrate optionality actually accrues to shareholders. 7741 Hoya operates at structural chokepoints — EUV mask blanks (75%+ share), ~100% consumer HDD glass — at 29.5% operating margin / ~21% ROE / wide moat. 5214 NEG is the purest display-glass-oligopoly play (#3 behind Corning, competes on cost, 11.0% OPM / ~10% ROE) with the GC Core semiconductor-glass-substrate optionality (mass-production target 2028, pre-revenue). 5201 AGC is a diversified materials conglomerate (6.2% OPM / ~5% ROE) where the high-quality electronic-materials/EUV-mask-blank niches are diluted by commodity architectural and automotive glass. For glass-substrate exposure specifically, NEG carries the most direct optionality (GC Core), but none of the three is a pure-play — packaging glass is a small slice of forward growth for each.

The OSAT / SiP / silicon-photonics chain — margins rise left to right

This is the heterogeneous-integration value chain: the layer where dies of different technologies (GaAs PAs, silicon controllers, SAW/BAW filters, GPU dies, HBM, InP lasers) are physically assembled into modules. The chain:

Raw materials (silicon, GaAs, InP, SAW/BAW crystals, epoxy, copper)
    ↓
Fabs (TSMC, Intel, GF, Tower, Soitec for SOI, Hoya for photomasks)
    ↓
Substrates (Unimicron, Nan Ya PCB, Shinko, Kinsus, AT&S, Ibiden)
Lasers & filters (Coherent, Lumentum, II-VI, Murata, Qualcomm, Broadcom filter biz)
    ↓
★ OSAT / packaging (ASE, Amkor, JCET, Powertech, USI, ShunSin, Fabrinet)
    ↓
Module integrator / RF IDM (Skyworks, Qorvo, Murata, Qualcomm-TDK, Broadcom)
    ↓
OEM / hyperscaler (Apple, Samsung, Xiaomi | AWS, Google, Microsoft, Meta)

The OSAT layer has three sub-markets with a clean margin gradient — margins rise from left to right: commodity OSAT ~12% GM → SiP ~15-18% → optical/FAU 20-30%+. Commodity OSAT (wirebond, leadframe, flip-chip BGA) is dominated by ASE, Amkor, JCET. Specialty SiP/RF module assembly is USI (ASE sub, the #1 merchant SiP house, ~$7B revenue / ~17% EBITDA), Amkor auto SiP, ShunSin, Nepes. Optical/silicon-photonics is Fabrinet (the biggest contract optical assembly house, ~$3B revenue / ~12% GM), ShunSin (emerging FAU-attach), and a handful of Asian specialty houses.

OSAT industry structure 2024 (top 10, global revenue $41.6B, +3% YoY):

#	Company	Ticker	2024 Rev ($B)	Share
1	ASE Technology	3711.TW / ASX	18.5	44.6%
2	Amkor	AMKR	6.3	15.2%
3	JCET	600584.SS	5.0	12.0%
4	Powertech	6239.TW	~2.9	7.0%
5	TFME (Tongfu)	002185.SZ	~2.3	5.5%
6	Huatian	002185 (verify)	~2.0	4.8%
7	WiseRoad	private	~1.5	3.7%
8	Hana Micron	067310.KS	~0.9	2.2%
9	KYEC (King Yuan)	2449.TW	~0.9	2.2%
10	ChipMOS	IMOS	0.7	1.7%

The margin-uplift rank order 2026-28 is the core investment question for this chain: CPO > advanced pkg (CoWoS class) > HBM test > SiP > commodity OSAT. Cross-industry cycle position (April 2026): commodity OSAT mid-cycle/balanced; specialty SiP mid-cycle/tight; RF FEM mid-cycle/balanced; memory packaging mid-to-late/tight on HBM3E/HBM4; test (KYEC) early-cycle-up/constrained (HBM test time 3x DRAM); advanced pkg (CoWoS/CoWoP) early-cycle/very tight through 2026; optical pluggables mid-cycle/balanced; CPO/SiPh early/very tight FAU capacity.

RF FEM and SiP BOM economics

RF content per smartphone rose from ~$15 BOM (4G) to ~$35-40 (5G+Wi-Fi 7+UWB+satellite). The RF FEM TAM is $29B in 2025 → $54B by 2030 (13% CAGR) — driven by content-per-device growth, not unit growth (handset units flat). Per-module BOM: RF front-end modules $3-8; Wi-Fi front-end modules $1-4. The IDM/packager split is the key margin-capture fact: the RF IDMs (Skyworks, Qorvo — now merging in a $22B deal — Broadcom, Qualcomm-TDK, Murata) do most of their packaging in-house, so merchant OSAT captures only secondary sockets and overflow capacity. ShunSin's RF work is exactly that — secondary Chinese Android FEM, connectivity, Wi-Fi FEM, plus overflow from the Foxconn iPhone assembly channel.

Silicon photonics / CPO economics and the FAU bottleneck

AI switch bandwidth scaling (25.6T → 51.2T → 102.4T → 204.8T) makes electrical interconnect off the switch ASIC unacceptable above 51.2T, forcing optics next to the ASIC. The hard, yield-limiting steps in optical packaging: laser attach (flip-chip InP onto SiPh substrate, sub-micron alignment) and — the single highest-skill step in the whole chain — FAU (Fiber Array Unit) attach: sub-micron precision, where 200nm misalignment costs 1 dB of insertion loss. This is why only a few houses can do it and why FAU capacity is the tightest sub-segment in the entire packaging complex.

CPO economics: a 51.2T module integrates ~64× 800G channels; finished module ASP $3,000-5,000; assembly/test margin capture at the OSAT layer is 20-35% GM at scale. Per-channel volume is smaller than pluggable (one CPO module replaces 32 pluggables on a faceplate) but per-unit dollar content is much higher and the process is harder. The adoption risk: CPO has been "2 years away for 5 years"; pluggables at 1.6T per-channel narrow the power advantage; hyperscalers have paused/restarted CPO programs repeatedly. TSMC's COUPE (insourced SiPh) is the structural threat to the merchant opportunity — but TSMC CoWoS is booked through 2026, so spillover to merchant OSATs is probable for the first generations.

OSAT capital intensity: capex/revenue ~10-15% normal, 20%+ in cycle-up years; a modern advanced-packaging line costs $100-300M; hyperscaler qualification takes 12-18 months; redesigning a CPO module to a new assembler is a 6-9 month requalification — so switching costs mid-program are extremely high. ASE's CoWoP and CoWoS capacity tripling (~20-25k wafers/mo by end-2025) is the single biggest OSAT-level capex event. Chinese OSATs (JCET, TFME, Huatian) build aggressively with state backing but are constrained from Western hyperscalers by export controls and customer preference for non-China capacity.

The silicon-capacitor thread and the EMIB turnkey choke point

Silicon capacitors are the newest bottleneck threading through the substrate chain. As packaging moves to 2.5D (Intel EMIB, TSMC CoWoS-S, Samsung I-Cube), power delivery must sit as close to the silicon as the package allows — MLCC on the PCB or even on the package top is too far for the highest-frequency rails, so silicon capacitors sit embedded in the bridge, interposer, or ABF substrate. Four qualified suppliers: Murata (acquired IPDiA 2016, Caen France), Samsung Electro-Mechanics (in-house), AP Memory (Taiwanese, TSMC fab partnership), and TSMC itself (IPD on advanced nodes). Murata and TSMC have internal demand from their own packaging — leaving SEMCO and AP Memory as the merchant suppliers with the most addressable external order book.

The value-chain reason this market is suddenly opening: per Jukan (@jukan05), TSMC's overwhelming share in AI-packaging substrates plus its in-house silicon-cap sourcing historically made it "effectively impossible for silicon capacitor suppliers outside of TSMC to break into the AI packaging value chain." Intel's EMIB rise breaks that — Intel cannot make its own silicon capacitors and must source externally. The choke point and pricing-power insight: within Intel's EMIB BOM the highest-value-added component is the substrate, so a supplier who delivers both the substrate and the silicon capacitor on a turnkey basis maximizes bargaining power. SEMCO is the only company in the world operating both a silicon-capacitor business and a substrate business — which is why it landed a >$1B supply contract (W1.6T 2-year order, Jan 2027-Dec 2028, likely Google v8e) off a prior-year silicon-cap revenue of "a mere few million dollars." Murata's counter-position is its close relationship with Ibiden (Intel's first-vendor substrate supplier); AP Memory's is its TSMC packaging relationship (CoWoS-S/L adjacency). Demand step-change drivers: Google v8e TPU (2H 2027, EMIB with embedded silicon caps), Intel EMIB scale-up from 2027 (Microsoft Maia, Amazon Trainium, NVIDIA networking), Amazon Trainium/Inferentia via Intel. The supply tightness is real — SEMCO is demolishing the parking lot around its existing plant to build a new fab because ABF substrate demand left no greenfield space.

Cross-chain convergence — the routing migration is the meta-bottleneck

The four chains are not independent — they compete for the same high-speed routing dollars. The most under-appreciated dynamic is the migration of high-speed routing between PCB, substrate, and optics. Glass substrate displaces the highest-frequency PCB routes that move up into the substrate; co-packaged optics displaces a fraction of the highest-loss high-speed PCB traces with optical waveguides; substrate tightness flows back into glass cloth (the same material, just T-glass instead of E-glass). Whoever wins each generation depends on physics + cost + ecosystem readiness, and the PCB layer has had more sustained demand than consensus models because routing projected to move to optics by now hasn't. The net effect of photonic integration on PCB demand is neutral-to-slightly-positive (smaller area, higher complexity/ASP, surviving electrical traces even more performance-critical), and the glass-core substrate transition is a substrate story that affects Ibiden/Unimicron mix rather than the PCB layer directly.

The capex-cascade playbook is identical across all four chains and traces four derivatives of beneficiary: (1) direct recipient — the fabricator with the AI win; (2) near-competitors/alt-suppliers absorbing overflow; (3) upstream components/tools/substrates; (4) second-derivative capex cycle — the materials and equipment makers whose capacity expansion is itself a third-derivative trade. The repeating LITE/COHR pattern (NVDA EML pre-allocation → upstream optics +955% in 2024) is the template: the multibagger has historically lived in the small-cap, single-feature, upstream-squeeze names — Fulltech in PCB, MEC/Mitsui in the substrate sub-layer, E&R in glass-core — though by mid-2026 several of those (Mitsui +11.8x, MEC +3.4x, Ibiden +6.7x) had already moved, shifting the trade from initiation to disciplined re-entry on pullbacks.

Players

Advanced packaging is not one industry but a stack of layers, and the players sort by which layer they own — glass material, copper foil, dielectric resin, surface chemistry, TGV/lamination equipment, CCL, the substrate fabricators, the OSATs, the silicon-capacitor suppliers, and the end customers. The recurring analytical pattern across every primer is the same: the named downstream beneficiary (the PCB fab, the substrate maker, the OSAT) is fully priced, while the bottleneck sits one or two layers upstream in a near-monopoly material or chemistry. Below, players are grouped by layer, with positioning and the investment angle. Company-specific deep detail lives on the ticker pages — this is the comparative view.

Glass material producers (substrate core + glass cloth)

The specialty-glass layer is a 4-5 firm global oligopoly. For glass-core substrate it is the foundational material; for AI-server CCL it is the woven glass cloth reinforcement. Packaging glass is incremental rather than transformative for most of these names, which is why exposure is diluted at the parent level.

• AGC / Asahi Glass 5201 — Japan glass + chemical conglomerate, ~$8.8B-$10B cap. Diversified across architectural (~25%), automotive (~20%), display glass (~10%), electronic materials incl. EUV mask blanks (~8%), chlor-alkali/fluorochemicals (~27%), biopharma CDMO (~7%). Display substrate #2 behind Corning; emerging packaging-glass position. The cheapest of the Japanese triad on P/B (0.91x) but lowest ROE (~5%) — "cheap for a reason," a 5% ROE conglomerate roughly breakeven against its cost of capital. Best held as dividend ballast (~4.3% yield) / sum-of-parts option, not a glass-substrate pure-play.
• Nippon Electric Glass (NEG) 5214 — Japan specialty glass, ~$3.1B-$3.5B cap, the purest display-glass play (the #3 price competitor in the 3-player display oligopoly, ~5-10% under Corning). Net cash, 70% equity ratio, aggressive 100B yen buyback (~21% of cap, running through 2028). T-glass position plus an emerging semiconductor glass-substrate business (GC Core, glass-ceramic substrates, pre-revenue, mass-production target 2028). The "get paid to wait" name: 11.8% total shareholder yield with a free option on the GC Core pivot. Best near-term risk/reward of the triad.
• Hoya 7741 — Japan precision optics, ~$62B cap, the highest-quality business in the triad by a wide margin. Two engines: Life Care (~64%, eyeglass/contact lenses, endoscopes, IOLs) and Information Technology (~36%, EUV mask blanks at 75%+ dominant share, ~100% consumer HDD glass substrates, FPD photomasks). IT segment ran 54.1% operating margin in FY2024. ROE ~21%, wide moat, 100% of FCF returned (547B yen buybacks in 6 years). Adjacent to packaging via photomask glass, some packaging-glass exposure. Expensive (~32x trailing P/E, 8.9x P/B) but reasonable on PEG (~2.0-2.3x) because the growth is durable. The compounder of the group.
• Corning (GLW) — US glass leader, ~$32B cap. OLED, optical fiber, Gorilla, photomask, packaging glass. Likely a primary packaging-glass supplier but reveals only at high level; packaging substrate alone won't move the stock. Watchlist-only as a glass-substrate proxy. The technology leader in display glass (superior fusion-draw process vs AGC/NEG).
• Schott (private, Zeiss Foundation) — German specialty glass, strong tech, no direct exposure. Named in the Trendforce underlying report alongside EV Group.
• Nittobo (3110.T) — Japanese fiberglass yarn + cloth, the glass-cloth tech leader, ~$3.5B cap. The single most important AI-server-PCB supply event: strategic exit from ultra-thin E-glass to focus on LDK/T-glass, which structurally withdraws capacity from the layer everyone downstream depends on. E-glass thin-fabric prices up ~30% YTD (April 2026) with another doubling priced in. Diversified parent dilutes the pure-play. Higher-quality but more diluted than Fulltech as the glass-cloth bottleneck.
• Fulltech (1815.TW) — Taiwanese fiberglass, ~$0.6B cap, 30-40% E-glass / 60-70% LDK. The named glass-cloth bottleneck pure-play and the highest-alpha-conviction name across the AI-server-PCB stack. Direct beneficiary of the Nittobo E-glass exit; long history in ultra-thin fabric (exactly the spec going short); projected 2H26 LDK2 supply gap of 2M+ meters/month per Taiwan Optical Electronics. Sell-side EPS NT$6-8 in 2026 / ~NT$10 in 2027 (Collyer Bridge). Single-product, small-cap, volatile. Top of the follow-up list. Alt play: Unitika (3103.T), flagged by Collyer Bridge but supply-chain feedback "not very good" — trade only. Other cloth names: Taiwan Glass (1802.TW), Owens Corning, AGY, Asahi Kasei.

The 5201/5214/7741 head-to-head is fully developed in _compare/5201-vs-5214-vs-7741-showdown.md ("Stock Showdown: AGC vs. Nippon Electric Glass vs. Hoya," March 2026). The composite scorecard:

Dimension (Weight)	AGC	NEG	Hoya
Business Quality (20%)	2.5	3.0	5.0
Financial Health (10%)	4.0	4.5	5.0
Growth (20%)	2.0	2.5	4.5
Valuation (15%)	4.0	3.0	2.0
Capital Allocation (10%)	2.5	4.0	4.5
Competitive Moat (15%)	2.5	3.0	5.0
Risk (5%)	3.5	2.5	3.0
Technical Setup (5%)	3.5	3.0	2.5
Weighted Total	2.85	3.10	4.10

Ranking from that showdown: 1) Hoya (best business, by far); 2) NEG (best risk/reward at current prices); 3) AGC (cheapest, but cheap for a reason). Suggested basket if owning all three: ~50-60% Hoya / 25-30% NEG / 10-20% AGC — though the author's own action was 60% Hoya, 30% NEG, skip AGC entirely as a value trap.

Copper foil

The premium circuit-foil layer is a near-monopoly at the top tier and the cleanest hidden-franchise in the AI substrate stack.

• Mitsui Kinzoku / Mitsui Mining & Smelting (5706.T) — >90% global share in MicroThin carrier foil (the only product qualified for ABF fine-line RDL at scale) and ~50% in mid-tier HVLP, hidden inside a zinc/lead/Cu smelter + auto-catalyst conglomerate (Cu foil ~5-14% of group). Group revenue ¥729B; ¥2.9T (~$19B) cap. Up 1,168% / 11.8x in 12 months as the market belatedly SOP-discovered the foil franchise. The structural thesis is the re-rating of the foil sub-segment from a smelter multiple to a specialty-chem multiple — "visible but not complete" at today's price. Korean (SK Nexilis, Iljin) and Chinese (Nuode) H-VLP3 catch-up is 18-36 months out at the second tier, not at MicroThin. Ikenobu Seiji succession (eff. Apr 1, 2026) lands a copper-foil-native CEO at the AI inflection. The COHR-equivalent of the Cu-resin stack.
• Furukawa Electric (5801.T) — Cu foil (LP/HVLP) + cables, ~$5B cap, ~15-20% HVLP share. Tier-2 player that benefits if Mitsui hits its capacity ceiling; conglomerate wrapper worse than Mitsui's. Low conviction.
• Iljin Materials (020150.KS) / SK Nexilis (009070.KS) — Korean HVLP/battery-foil makers racing to qualify at the AI substrate tier, ~18-24 months behind Mitsui. Battery-foil overhang dominates the story; substrate foil is the option, not the base case. Avoid at current prices.
• Nuode (600110.SH) — Chinese HVLP entry, quality 12-18 months behind but lower cost; risk is China-only qualification under export-control denial.
• Standard ED foil (commodity, ~10-15% GM): Furukawa, Nippon Denkai, Iljin, Lien Yu (Chang Chun Group).

Dielectric resin

The most concentrated and most acute single-vendor risk in the entire AI supply chain.

• Ajinomoto (2802.T) — ABF (Ajinomoto Build-up Film), >90% of advanced organic substrates globally, hidden inside a food/healthcare/amino-acid conglomerate (~$20B cap; ABF ~5% of revenue). Three-decade head start on a chemistry never displaced; spec-lock at substrate fabs is total. Not a Pink-actionable pure-play — food businesses trade at staples multiples and won't re-rate, so the SOP arbitrage is durable but doesn't unwind on retail timeframes. Reference position only. Single-vendor concentration is the structural risk: a 2020 Kanagawa-plant fire caused a 90-day shortage; a repeat today would halt the AI substrate ramp for a quarter.
• Sekisui Chemical (4204.T) — SEKIRES low-Dk PI dielectric film, the most credible non-Ajinomoto resin challenger but <5% share, trailing-edge use. Vera-Rubin-era qualification possible only if Ajinomoto's next-gen GZ-N misses targets. A 0.5%-position tracker, not a thesis.
• Resonac / Showa Denko (4004.T) — photo-dielectric film for RDL fine-line / FOWLP. Niche.
• PPO/PPE resin (the matrix in low-loss CCL): SABIC (~70% global, listed parent 2010.SR) plus DIC and Asahi Kasei. SABIC lost 25-30% of Saudi PPO capacity to a gas constraint in April 2026 — a single-supplier dress rehearsal. BT resin: Mitsubishi Gas Chemical (4182.T), DIC. Long-loss PI/hybrid R&D: Kaneka, UBE.

Surface chemistry (Cu-to-resin adhesion)

The highest gross margin in the substrate stack and the layer the market has priced least.

• MEC Company (4971.T) — CZ-series copper microetchant, ~100% share in PC CPU substrate Cu adhesion (>20 years) and ~70-80% in advanced server/AI substrate, plus next-gen AP-series (no-roughening adhesion for sub-2µm RDL). ¥12B revenue / ¥204B (~$1.3B) cap; 62% gross margin, the highest in the chain. Up 340% / 3.4x in 12 months. The moat is spec lock (every fab carries CZ-8101 in its qualification document; swapping triggers a 12-24-month re-qual), not patent IP. CZ-8101 qualified into CoWoS chiplet packaging. Growth is rate-limited by capacity, not demand. The mispriced option no one is paying for is the AP-series next-platform extension. The LITE-equivalent of the Cu-resin stack. Quality A+, entry F — WATCH at ¥7-9k.
• Desmear / electroless-Cu / surface finish (2-3 vendor oligopoly): Atotech (now an MKS subsidiary, ~40% surface finish), Uyemura (4966.T) (~20-25%, ~$800M cap, the closest pure-play), Okuno, Dow/Rohm & Haas.

Solder mask / build-up dielectric (final-layer)

• Taiyo Holdings / Taiyo Ink (4626.T) — PSR (photo-imageable solder resist), ~60-70% share, spec-locked, ¥300B (~$2B) cap. The AI angle is Rubin-substrate dry-film exclusivity: per STF Research, B200 dry-film attach rate jumps 50% → 90% and Rubin = 100% dry film; Zaristo dry film carries a 30-50% ASP premium vs liquid ink. FPIM (Fine Pitch Insulating Material) is a Taiyo + imec co-development monopoly for Rubin's HBM4 logic-base-die <2µm RDL — STF claims earnings power could double the current implied price over 3 years. A consensus pick within the materials stack — bottleneck-tier but less alpha than MEC or Mitsui Kinzoku.

TGV / lamination / drilling equipment

The highest-leverage bottleneck for glass-core substrate (TGV) and a hidden champion in lamination.

• E&R Engineering (8027.TWO) 8027 — TGV laser + plasma equipment, validated for glass-core substrate in 2024 after a 5-year co-development with a North American IDM (implied Intel via a Japanese substrate-maker intermediary). The TGV customer is the Japanese substrate maker, not Intel directly; validation accelerating, small production 2026, scaling 2027. AIS (Automation Integration Service) is a separate North American revenue stream with orders into 2027. ~$0.5B cap, Tw$1.81B FY2025 revenue, loss-making FY2024-2025, 9x EV/Sales on ~$55M revenue, single-analyst PT TWD 98 vs TWD 156. Essentially a real option on glass-core deployment — the only public small-cap pure-play with a validated TGV process; highest purity in the equipment layer. Size as a real option, not a compounder.
• LPKF Laser & Electronics (LPK.DE) — German specialist laser systems (LDS for 3D antennas, plus TGV and PCB laser drilling). ~$0.3B-€696m cap (re-rated 4.8x YTD by 8 May 2026 to €28.40). Active glass-substrate development but a shallower public footprint than E&R; the trade reframes as binary on the 23 July 2026 H1 print (first major LIDE order disclosure). The Trendforce-cited "small-cap call" — but that ~$150m MC framing is now stale. Tier 2 — less pure-play than E&R, more diversified, mobile/auto cyclicality drags the multiple.
• DISCO (6146.T) — world leader in semiconductor singulation/cutting, ~$25B cap. Glass singulation is a strong adjacency; diversified across semicap.
• Kitagawa Seiki (6327.T) — vacuum press for CCL/multi-layer lamination, world #1, small-mid cap. The hidden champion per STF Research: Q1 FY2026 order intake ¥5.4B (10-year high), gross margin 27.2% → 31.9% YoY, PCB share of backlog 68% → 85%. Sole supplier qualified for M9/Q-Glass tolerances — as Vera Rubin moves to M9 + Q-Glass the processing window narrows and second-tier presses can't hold tolerance on $30-50K boards. No English sell-side coverage = mispricing. Strong alpha conviction.
• Union Tool (6278.T) — micro-drill bits, 30-40% global share, ~$1.9B cap. Toll-booth/razor-blade economics on PCB volume; love the business, hate the price (re-rated 5x). Watch for a pullback to ¥10-12K.
• Other equipment: laser sources MKS Instruments (MKSI) / Coherent (COHR) / Trumpf (private); via metallization Applied Materials (AMAT), Lam Research (LRCX), TEL (8035.T), Tango Systems (private US TGV specialist); drill machines Mitsubishi Electric (6503.T, CO2 laser, ~70% top-2 share), Via Mechanics (Hitachi sub), Schmoll, Posalux; AOI inspection Camtek (CAMT), Orbotech/Nordson (NDSN), ONTO ONTO, KLAC; bonding SUSS MicroTec (SMHSF). The Trendforce 2026-05-11 name-drop (glass-substrate "leading players") confirmed LPK, GLW, ASGLY/5201, NIDGY/5214, LRCX, DSCSY/6146, SMHSF, ONTO, KLAC — all already in the primer value chain; no new names.

CCL (copper-clad laminate)

• Shengyi Tech (600183.SH) — China #1 CCL, ~$25B cap, pushing into premium Megtron-equivalent grades. Direct beneficiary of glass-cloth + PPO tightness flowing into margin; the closest investable proxy for premium-CCL (M7N/8/M9) pricing power. China-domestic AI (Ascend) catalyst independent of NVIDIA. Premium-grade qualification still maturing; some Western customers resistant.
• Elite Material (2383.TW) — Taiwan #1 CCL, ~$10B, mainstream + low-loss.
• ITEQ (6213.TW) — Taiwan high-end CCL, ~$4B, strong AI-server exposure (IT-988GSE).
• TUC / Taiwan Union Tech (6274.TW) — mid-tier, ~$3B.
• Panasonic Megtron (parent 6752.T) — the de facto standard premium AI CCL (Megtron 6/7/7N/8); M8 essentially Panasonic-alone today with Shengyi catching up. Not directly investable — high-margin but small inside a ¥3T conglomerate. Analytical anchor only.
• Others: EMC (1909.TW), Mitsubishi Gas Chemical (4182.T, BT resin/substrate CCL), Doosan (000150.KS), TUC.

Substrate fabricators (ABF FCBGA + glass-core transition)

The 5-firm oligopoly that consumes the foil, resin, and chemistry above — and the layer most exposed to either winning or losing the organic-to-glass-core transition. This layer is fully priced; the alpha is upstream.

• Ibiden (4062.T) — #1 global ABF substrate (~30-35% share, ~40-50% of flagship Vera-Rubin-class volume), ~$10B-$30B cap depending on date, Intel first-vendor. The substrate maker most exposed to the glass-core transition: most to lose from organic displacement, most to gain from owning it, deepest Intel relationship to make migration commercial. Contrarian Oono Phase 1+2 capex (¥250-300B 2022-2024) aged perfectly into the AI substrate area explosion. Up 570% / 6.7x in 12 months. The clearest direct AI-substrate exposure but the consensus catch-up trade is symmetric — pass on initiation, track for sell-side PT revisions. The best public proxy for glass-core fabrication (no public pure-play exists there). WATCH at ¥14-14.5k.
• Shinko Electric (6967.T) — #2 ABF substrate, FCBGA leader, ~20-25% share, ~$6B cap. Less public glass-core exposure; needs to follow Ibiden.
• Unimicron (3037.TW) — Taiwanese ABF substrate + advanced PCB, ~$9-10B, ~20-25% substrate share, one of <5 makers with ABF capability at AI-accelerator scale. Glass-core position uncertain (primarily ABF). Substrate-tightness play; substrate tilts the mix.
• AT&S ATS — Austrian/European #5 ABF substrate (~5-8% share), ~€1.5B cap, AMD anchor, Kulim Malaysia ramp (partially CHIPS-funded). The substrate-transition risk name: if glass-core migration accelerates faster than 2030, AT&S faces structural high-end growth pressure unless it commits substantial glass capital; the conservative AMD anchor partially insulates. Bull is ABF cycle re-acceleration 2026-2027 regardless of glass timing.
• Samsung Electro-Mechanics / SEMCO (009150.KS) — Korean substrate + components, ~$8-10B group cap, ~10-12% substrate share. Heavy R&D into glass-core; potential primary supplier for hyperscaler custom silicon. Also the breakout silicon-capacitor story (see below). A sum-of-segments framework (MLCC + FC-BGA + silicon capacitor + camera modules + net cash) lands at gross SOTP of W60-63T (implied ~KRW 825-870K) under moderate assumptions; even the aggressive bull case (~KRW 1.25M, lifted to ~KRW 1.4-1.5M with the EMIB turnkey premium) is still 20-32% below the current KRW 1.85M.
• Daeduck Electronics (008060.KS) — Korean substrate maker, ~$1B, some glass-core development.
• Kinsus (3189.TW) — Taiwanese substrate, ~$2B, limited glass exposure.
• Nan Ya PCB (8046.TW) — Taiwanese ABF substrate + PCB, ~$2.5B, limited glass exposure.
• Simmtech (222800.KQ), Foxconn (2317.TW, panel-level packaging, tangential), and Chinese substrate adjacencies (Shennan/Suntak) round out the tail; Chinese makers face 2028-2030 commercial qualification at earliest given US-origin tooling export-control barriers.

AI-server PCB fabricators

The "named" downstream winners — great businesses, real share gains, but where consensus has already priced the AI bull case. A tactical share-shift trade, not a pricing-power trade.

• Victory Giant (002476.SZ / 2476.HK) — pure-play advanced PCB, ~$28-30B cap, >70% AI revenue mix (highest in the peer set). Went from #7 at 1.7% global AI/HPC PCB share (2024) to #1 at 13.8% (H1 2025) — a 10x share gain in 12 months, +600% in 2025. First Chinese fab into NVIDIA's primary accelerator board at AI-grade quality; geographic-decoupling hedge via Thailand (APCB) + Vietnam ($520M Bac Ninh). 2024: revenue CN¥10.73B, NI CN¥1.15B. Concentration risk on NVIDIA; little margin of safety post-rerate. Full deep-dive at KB/wiki/002476/002476.md.
• Shennan Circuits (002916.SZ) — the most diversified Chinese PCB peer (~$15-18B, 40-50% AI mix): AI server + networking + IC substrate + automotive, Huawei/ZTE relationships plus AI wins. Less explosive share story than Victory Giant; substrate business adds a high-margin optionality layer. Wait for AI mix to reach 50%+.
• Tripod (3044.TW) — Taiwanese fab, ~$8B, rumored primary NVSwitch-tray supplier (per Collyer Bridge), plus CSP/optical boards. Direct play on NVSwitch-tray volume per rack; potential beneficiary of the NVIDIA PCB-for-Amphenol-overpass-connector replacement story. Heavy NVIDIA concentration, limited customer-mix disclosure.
• Others: Suntak (002815.SZ, ~30% AI), Aoshikang (002913.SZ, ~30%), Compeq (2313.TW, HDI/optical), GCE/Gold Circuit (2368.TW), plus emerging Wus (Kunshan, private), Bomin (private TW), Senior PCB (300476.SZ). Anylayer HDI — the real fab-tier moat (<10 fabs worldwide) — sits with Victory Giant, Unimicron, Tripod, Ibiden, Compeq, AT&S. Western fabs (Sanmina, TTM, AT&S in mil-aero) can't win AI-server volume.

OSAT / SiP / RF / silicon photonics

The contract integrators of heterogeneous packaging. Top-10 OSAT global revenue was US$41.6B in 2024 (+3% YoY, TrendForce):

#	Company	Ticker	2024 Rev (US$B)	Share
1	ASE Technology	3711.TW / ASX	18.5	44.6%
2	Amkor	AMKR	6.3	15.2%
3	JCET	600584.SS	5.0	12.0%
4	Powertech	6239.TW	~2.9	7.0%
5	TFME (Tongfu)	002185.SZ	~2.3	5.5%
6	Huatian	002185.SZ (code conflict — verify)	~2.0	4.8%
7	WiseRoad	private	~1.5	3.7%
8	Hana Micron	067310.KS	~0.9	2.2%
9	KYEC (King Yuan)	2449.TW	~0.9	2.2%
10	ChipMOS	IMOS	0.7	1.7%

• ASE Technology (3711.TW) — world #1 OSAT (44.6% share), does SiP directly and via USI. CoWoP (CoWoS-on-PCB) and CoWoS capacity tripling (~20-25k wafers/mo by end-2025) is the single biggest OSAT-level capex event. The liquid, diversified cycle play.
• Amkor (AMKR) AMKR — global #2 OSAT (15.2% share), distant #3 in SiP, strong in automotive modules (radar SiP, camera SiP). Liquid cycle play alongside ASE. 2.4x EV/Revenue, 14.8x EV/EBITDA, +16% rev growth (April 2026).
• JCET (600584.SS) — #3 OSAT, Chinese, state-backed capacity build; constrained from Western hyperscalers by export controls/customer preference. 2.2x EV/Revenue, -7% rev growth.
• Powertech (6239.TW) — #4 OSAT, memory packaging (DRAM/flash/HBM SiP), +25% rev growth, 9.0x EV/EBITDA.
• KYEC / King Yuan (2449.TW) — test pure-play, #9 OSAT; the AI/HBM-test tailwind (HBM test time ~3x DRAM) drove a re-rating. Best-margin OSAT (46% EBITDA margin) — already re-rated; 10.1x EV/Revenue, 21.6x EV/EBITDA, +37% rev growth. The HBM/AI-test pure-play.
• USI / Universal Scientific (601231.SH, ASE sub) — #1 merchant SiP house globally (Apple Watch S-series, AirPods, AR), ~US$7B rev, ~17% EBITDA margin. The quality merchant-SiP comp.
• ShunSin (6451.TW) — Foxconn-channel specialty (~US$230M): RF-SiP/MEMS for Chinese Android + emerging FAU-attach in the NVIDIA/Broadcom CPO supply chain (~US$145M optical segment, scaling). The speculative tier — 7.5x EV/Revenue / 68.8x EV/EBITDA priced for CPO/SiPh optionality, not its 11% EBITDA margin.
• Fabrinet (FN) — the biggest contract optical-assembly house (~US$3B rev), mature FAU-attach, hyperscaler-qualified, ~12% GM. The optical-packaging anchor.
• RF-FEM IDMs (mostly in-house packaging, merchant OSAT gets overflow): Skyworks (SWKS), Qorvo (QRVO) — the two announced a US$22B merger in 2025 — Broadcom (AVGO), Qualcomm-TDK RF360 JV, Murata (6981.T). RF content per phone rose from ~$15 (4G) to ~$35-40 (5G+); RF-FEM TAM US$29B (2025) → US$54B (2030), 13% CAGR, content-driven not unit-driven.
• Chinese pluggable-transceiver pure-plays: Innolight (300308.SZ), Eoptolink (300502.SZ), US$1-3B rev, 30%+ GM. Laser/module IDMs: Coherent (COHR), Lumentum (LITE). TSMC's COUPE and CoWoS (booked through 2026) is the insourcing risk to merchant optical OSATs — but constrained TSMC capacity means first-gen spillover.

OSAT trading multiples snapshot (April 2026): ASE 3.3x EV/Rev / 18.4x EV/EBITDA; AMKR 2.4x / 14.8x; JCET 2.2x / 14.2x; Powertech 2.5x / 9.0x; KYEC 10.1x / 21.6x; ChipMOS 1.4x / 5.7x; ShunSin 7.5x / 68.8x; Fabrinet ~2.7x / ~19x; Coherent ~3.5x / ~18x. The two EV/Revenue outliers are KYEC and ShunSin — both "paid for the narrative," but only KYEC's current prints justify the multiple.

Silicon-capacitor suppliers

The newest bottleneck — chip-form capacitors fabricated on silicon wafers, embedded in 2.5D bridges/interposers/ABF for power delivery close to the die. Four qualified suppliers; Murata and TSMC have internal demand, leaving SEMCO and AP Memory as the merchant suppliers with the most addressable external order book.

• Murata (6981.T) — acquired IPDiA 2016, production in Caen, France; the incumbent leader, vertically integrated. Close Ibiden relationship (Intel's substrate first-vendor) positions it for EMIB.
• SEMCO / Samsung Electro-Mechanics (009150.KS) — the breakout name. Citi: silicon-cap revenue W609bn FY27E / W905bn FY28E, anchored by a W1.6T 2-year supply order (Jan 2027-Dec 2028) from a "major global company" (likely Google v8e). Already supplying Marvell. Per Jukan, SEMCO is the only company running both a silicon-capacitor and a substrate business — the structural moat is "the only turnkey substrate + silicon-cap bundle for Intel EMIB," a bargaining-power premium Murata (via Ibiden) and AP Memory (via TSMC) can't match. Capacity-constrained enough that it is demolishing a parking lot to build a new fab. Per Zephyr, silicon caps are experiencing supply tightness and "will likely pop off like MLCC players" — Murata/SEMCO/AP Memory have the highest exposure. (Note: Zephyr is an independent AI & Chips analyst, NOT affiliated with Citrini Research.)
• AP Memory (6531.TW) — Taiwanese, TSMC fab partnership; core business PSRAM/high-speed SRAM. Silicon-cap exposure is real and disclosed: discrete S-SiCap IPD (Gen3 production, Gen4 ramping 2026) + silicon-capacitor interposer IPC (four-reticle mass production from end-Q3 2025). Intel EMIB first-qualified-supplier May 21 2026 with Q2 2026 shipment start — serves Google v8e TPU (2H 2027), Microsoft Maia, Amazon Trainium; CoWoS-S/L adjacency at TSMC is additive. Silicon cap est. 15-25% of FY2025 NT$5.67B revenue (segment split not disclosed — the #1 valuation risk). Stock NT$1,080 (+365% in 13 months), 42x fwd PE, +39% above the MS raised PT NT$777. Canonical page: 6531. Verdict PASS at NT$1,080 / WATCH NT$650-800 / BUY NT$400-550.
• TSMC (2330.TW) — Integrated Passive Devices on advanced nodes; internal demand, sold as part of the foundry package, not separately reported.
• Adjacent: Vinatech (126340.KQ).

Demand-side anchors driving 2.5D/EMIB silicon-cap and substrate pull

Google v8e TPU (EMIB substrate with embedded silicon caps, 2H 2027), Intel EMIB scale-up from 2027 (covers Microsoft Maia, Amazon Trainium, NVIDIA networking, Intel's own products), Amazon Trainium/Inferentia via EMIB. End customers across the whole stack: Intel, NVIDIA, AMD, Google, Amazon, Microsoft, Meta — packaging through OSAT partners (Amkor, ASE, JCET, Powertech).

Cross-references

The Cu-resin sub-layer has its own management-alignment overlay in themes/cu-resin-swarm-incentive-screen.md, which screens 4971/4062/5706 (MEC, Ibiden, Mitsui Kinzoku) on guidance tendency, follow-through (85-100% all three), and incentive alignment (all three pass the mgmt-quality gate — differentiator pushed to business quality + entry price). The head-to-head head trade-off for those three lives at _compare/4971-vs-4062-vs-5706-showdown.md. The glass-triad head-to-head is _compare/5201-vs-5214-vs-7741-showdown.md. Companion primers: ai-server-pcb-primer.md, packaging-glass-substrate-primer.md, cu-wiring-resin-primer.md, silicon-capacitor-primer-2026-05-28.md, sip-osat-rf-primer.md. Ticker pages: 8027, 002476, 5201, 5214, 7741, ATS, AMKR, 6531, ONTO, LPKF.

Monitor

A rolling log of dated developments, catalysts, earnings signals, and standing watch-items across advanced packaging and substrates. The sector spans five interlocking sub-stacks — AI server PCB / CCL, the Cu-wiring-and-resin substrate sub-layer, glass-core IC substrate, silicon capacitors, and SiP / OSAT / silicon photonics — and the catalysts in each feed the others. Dated specifics are preserved with their dates. Company-specific deep dives live on ticker pages; this section tracks the industry-wide clock.

Dated developments (chronological)

September 2023 — Intel GlassCore announcement. At its packaging tech day Intel announced GlassCore, a research program targeting glass substrate IC packages by 2030, positioning glass to replace organic ABF. The market read it as a long-dated R&D talking point; two years later the supplier ecosystem began qualifying. See packaging-glass-substrate-primer.

2024 — E&R Engineering TGV validation. E&R Engineering (8027) validated TGV (through-glass via) laser processing for glass core substrates after a 5-year co-development with a North American IDM (implied Intel via a Japanese substrate-maker intermediary). The Japanese customer is "accelerating validation; small production 2026, scaling 2027."

2024 — Victory Giant share gain. Victory Giant went from #7 with 1.7% global AI/HPC PCB share in 2024 to #1 with 13.8% share in H1 2025 — a 10x share gain in 12 months. Up ~600% over 2025. See ai-server-pcb-primer.

2024 — Victory Giant decoupling moves. Thailand acquisition (APCB, 2024) and Vietnam plant ($520M Bac Ninh, started March 2025) to secure US-bound supply through non-China origin — a strategic decoupling play, not just cost.

2024 (Q4) — OSAT industry print. Top 10 OSATs at US$41.6B global revenue, +3% YoY per TrendForce; ASE #1 at 44.6% share. See sip-osat-rf-primer.

2025 — NVIDIA NVL72 / GB200 ships at scale. Each rack consumes more advanced PCB area than an entire smartphone factory's annual output; the PCB is the largest single non-silicon line item.

2025 — Nittobo signals E-glass exit. Nittobo, the world's most important fiberglass cloth maker, started telling customers it is exiting the ultra-thin high-end E-glass cloth used in AI server CCL, to focus on LDK and T-glass. This is a structural withdrawal of capacity from a tier everyone downstream depends on (Shengyi, Panasonic, ITEQ, Elite, Victory Giant, Unimicron, Ibiden).

2025 — Skyworks / Qorvo US$22B merger announced, consolidating the RF-FEM IDM landscape. Apple N1 chip (iPhone 17 Pro), Apple's first in-house Wi-Fi 7 + BT silicon, is the canonical in-sourcing example — Broadcom the loser, packaging flow still through Foxconn (neutral-to-positive for ShunSin).

Jan 7, 2026 — Goldman Sachs aggressively revises up AI PCB/CCL TAM (per STF Research, mirrored at KB/raw/substack-archive/stf-research/2026-01-07-gs-aggressively-revises-up-ai-pcb-ccl-tam.md): AI PCB TAM $26.6B in 2027 (up from prior $17.4B, ~140% CAGR 2025-27); AI CCL TAM $18.3B in 2027 (up from prior $8.0B, ~178% CAGR). Critically, growth accelerates in 2027 vs 2026 — second derivative positive, not topping out. Driver is Vera Rubin VR200/VR300 replacing bridge cables with PCBs/CCLs: midplane content per GPU rises to ~$171-256 (107%/57% jump vs GB300, starting 2H26); backplane content per GPU rises to ~$781-1,563 (5x/4.5x jump, starting 2H27). Yield erodes from ~73% to ~62% as layers move 24-28 → 40+ and HDI build-up moves 4+N+4 → 6+N+6, so CCL TAM grows faster than finished PCB TAM precisely because more material is scrapped.

Jan 31, 2026 — STF Research: Taiyo Holdings solder mask demand. Substrate area progression Hopper 3,025mm² → Blackwell 5,625mm² → Rubin 8,100mm². B200 dry-film attach rate jumps 50% → 90%; Rubin = 100% dry film. Taiyo's Zaristo dry film carries 30-50% ASP premium vs liquid ink. FPIM (Fine Pitch Insulating Material), co-developed with imec for Rubin's <2µm RDL on the HBM4 logic base die, is a Taiyo + imec monopoly; STF claims earnings power could double current implied price over 3 years.

Mar 16, 2026 — STF Research: Kitagawa Seiki "Hidden Champion Pressing the AI Era." Flags M9 + Q-Glass as Vera Rubin material. Kitagawa Seiki (6327.T), world #1 vacuum press for CCL/multi-layer lamination, posted Q1 FY2026 order intake ¥5.4B (10-year high); gross margin 27.2% → 31.9% YoY (+470bps); PCB share of backlog 68% → 85% YoY; sole supplier qualified for M9/Q-Glass tolerances. No English sell-side coverage — flagged as mispricing.

Mar 17, 2026 — Japanese glass triad showdown. AGC (5201.T) vs NEG (5214.T) vs Hoya (7741.T). All three sold off in early-to-mid March 2026 (tariff fears, global growth worries). Hoya rated best business (4.10/5 composite), NEG best near-term risk/reward at 0.94x book with 11.8% total shareholder yield, AGC cheapest but a 5% ROE value trap. NEG's GC Core glass-ceramic semiconductor substrate is pre-revenue with mass-production target 2028. See 5201-vs-5214-vs-7741-showdown and 7741, 5201, 5214.

April 2026 — Glass cloth + PPO resin double squeeze. E-glass thin fabric prices up ~30% YTD with market pricing in another doubling in 2026. Taiwan Optical Electronics forecasting a 2 million meters/month LDK2 supply gap by 2H26. Then in mid-April SABIC — which controls ~70% of world PPO resin supply — lost 25-30% of its Saudi capacity to a natural-gas constraint. PPO is the resin in low-loss CCL. Simultaneous shortage in both reinforcement (glass cloth) and matrix (PPO resin) of the AI server laminate. Flagged by Collyer Bridge / @illyquid APAC Wrap 17 April 2026.

April 2026 — NVIDIA evaluating PCB replacement for Amphenol overpass connector (per Global Tech Research). Suggests NVSwitch tray PCBs absorbing more of the rack's high-speed routing — bullish for advanced PCB volume per rack, and specifically for Tripod (3044.TW, rumored primary NVSwitch supplier) and Victory Giant.

Apr 20, 2026 — SiP / OSAT / RF primer written, triggered by the ShunSin (6451.TW) deep-dive. Cross-industry cycle snapshot: CoWoS / CoWoP and CPO / SiPh in very-tight early-cycle; KYEC test early-cycle-up; SiP / RF-FEM mid-cycle. TSMC CoWoS booked through 2026; ASE CoWoS capacity tripling to ~20-25k wafers/mo by end-2025. See sip-osat-rf-primer.

Apr 21, 2026 — Victory Giant HK debut +57.23%, US$2.6B raise (A/H listing 2476.HK, per Collyer Bridge APAC Wrap 21 April / Acid Investments). HK listing brings Western capital to the #1 AI/HPC PCB name.

24 April 2026 — Intel cites substrate, T-glass, and memory costs as gross-margin headwinds (Q1 2026 earnings). Intel is paying for the new glass-substrate material today, not in 2030 — the clearest signal that the R&D phase has ended and qualification is in flight. Per Collyer Bridge / @illyquid Intel Supply Chain Ideas (jukan05 quote).

May 11, 2026 — Trendforce glass-substrate name-drop confirms primer thesis. @aleabitoreddit (Serenity) cited a Trendforce report naming the same 9 listed glass-substrate players the packaging-glass-substrate-primer already mapped: LPKF, Corning, AGC, NEG, Lam Research, Disco, SUSS MicroTec, ONTO, KLAC (underlying report also names SCHOTT and EVG, both private). Third-party validation that the LIDE thesis is now widely held — not a fresh small-cap call. No new technology disclosures, no customer commits, no order numbers. Serenity's "~$150m MC" LPKF call from "early in the year" is stale: as of 8 May 2026 LPK.DE trades €28.40 / cap ~€696m (4.8x YTD). See glass-substrate-trendforce-2026-05-11 and LPKF.

May 12, 2026 — Cu wiring & resin primer + swarm. Mitsui Kinzoku (5706) up 1,168% / 11.8x in 12 months; MEC (4971) up 340% / 3.4x; Ibiden (4062) up 570% / 6.7x. The order matters — the market priced the fabricator first, then the foil, and has not yet priced the adhesion chemistry tier. Mitsui's premium Cu foil saw a 12% price hike in April 2026 with no pushback (pricing power confirmed). MEC CZ-8101 qualified into CoWoS chiplet packaging (Nippon-IBR Dec 2025 disclosure). See cu-wiring-resin-primer and cu-resin-swarm-incentive-screen.

May 13, 2026 — Mitsui Kinzoku (5706) FY26 initial guide (binary print). The buy trigger was FY26 OI guide ≥¥130B (Tranche 1 50% at ¥45-48k); walk-away was <¥120B; in-between was no-action. Feb 2026 raise already implied FY27 OI a year early. See 5706.

May 20, 2026 — SEMCO supplies silicon capacitors to Marvell (The Elec). See silicon-capacitor-primer-2026-05-28 and 009150.KS.

May 21, 2026 — AP Memory (6531) first-qualified Intel EMIB silicon-capacitor supplier, with Q2 2026 shipment start — serving Google v8e TPU (2H 2027), Microsoft Maia, Amazon Trainium. CoWoS-S (IPC interposer) + CoWoS-L (IPD discrete) adjacency at TSMC is additive. See 6531.

May 24, 2026 — Zephyr @zephyr_z9 silicon-capacitor supply-tightness PSA (34 retweets / 483 likes): "Silicon capacitors are experiencing supply tightness and will likely pop off like MLCC players. Murata, SEMCO, AP Memory have the highest exposure." Quote-tweeting Jukan: SEMCO tried to expand ABF substrate capacity but, lacking greenfield space, decided to demolish the parking lot around its existing plant to build a new fab there. Note: Zephyr is an independent AI & Chips analyst, NOT affiliated with Citrini Research (the "Z from Citrini" framing is a conflation). See passives-twitter-scrape-2026-05-28.

May 27, 2026 — GS Murata sell-side meeting. Murata acknowledged TSMC, SEMCO, and Murata all have silicon-capacitor tech.

May 28, 2026 — Jukan @jukan05 "Why Are Silicon Capacitors Becoming Important?" (46.5K views). The structural framing: silicon caps never grew because TSMC, with overwhelming AI-packaging substrate share, sourced them in-house — locking non-TSMC suppliers out. Intel EMIB changes this: Intel cannot make its own silicon caps and must source externally; the highest-value EMIB BoM component is the substrate; so a supplier delivering both substrate and silicon cap on a turnkey basis maximizes bargaining power. SEMCO is the only company running both a silicon-capacitor and a substrate business — hence the stock surge. SEMCO landed a >$1B contract despite last year's silicon-cap revenue being "a mere few million dollars." Murata stays close to Ibiden (Intel's first substrate vendor). See silicon-capacitor-primer-2026-05-28.

May 28, 2026 — Silicon capacitor primer + AP Memory profile written. Citi: SEMCO silicon-cap revenue W609bn FY27E / W905bn FY28E, anchored by W1.6T 2-year supply order (Jan 2027 - Dec 2028) from a "major global company" (likely Google v8e). AP Memory: silicon cap est. 15-25% of FY2025 NT$5.67B revenue; Gen3 S-SiCap IPD in production, Gen4 ramping 2026; IPC interposer in four-reticle mass production from end-Q3 2025; Q1 2026 total revenue +115% YoY. Stock NT$1,080 = +365% in 13 months / +160% in 8 weeks / 42x fwd PE / +39% above MS raised PT NT$777; verdict PASS at NT$1,080, WATCH NT$650-800, BUY NT$400-550.

Standing catalysts and tracking signals

The single most-cited industry tracking signal across the glass-substrate sources is first-production-line yield improvement at the Japanese substrate maker (E&R's customer) — year-over-year yield % is the leading indicator for the entire glass-core industry's commercial readiness. First-line yield is 30-50% today vs the 70-80% needed for commercial scale.

Named catalysts and the trigger to watch in each:

• Intel GlassCore production timeline — does the 2030 target accelerate to 2028-2029? Commercial-volume confirmation directly threatens organic ABF substrate at flagship tier post-2030; if Intel ships commercial volume in 2027-2028, ABF resin / Cu foil / CZ growth rates at the >100mm package tier revise down.
• NVIDIA Vera Rubin substrate decision (VR300 / Ultra) — glass core or stay with ABF. Drives the 2H27 demand step-up; layer count and line/space specs will set the MicroThin + AP-series volume rate.
• Second substrate-maker glass capex commit (Samsung Electro-Mechanics or AT&S) — a second qualified maker = 2x deployment certainty.
• Hyperscaler custom-silicon glass-core qualifications — Trainium 3, TPU v7 / v8e, Maia generations.
• TGV laser equipment competitive entry — Trumpf, Tango Systems scaling alongside E&R + LPKF.
• LPKF 23 July 2026 H1 print — reframed by the LPKF profile as the binary event on first major LIDE order disclosure.
• MEC AP-series customer disclosure — flagship-tier qualification at a substrate fab beyond MEC's existing disclosure re-rates the multiple higher; the option the market hasn't underwritten (justifies waiting for ¥7-9k entry). MEC Kitakyushu capacity expansion starts Dec 2026.
• Korean / Chinese H-VLP3 qualification at Ibiden or Unimicron — the moment a second source is qualified at flagship tier, Mitsui Kinzoku's premium-grade Cu foil pricing power compresses (qualification window 18-36 months out).
• Ajinomoto next-gen resin (GZ-N) qualification timing — if delayed or missed, Sekisui SEKIRES qualifies into the gap.
• SABIC Saudi PPO ramp-back timeline — April 2026 outage; if it stays out 6+ months, premium CCL margin spikes further.
• Fulltech LDK revenue share — does it hit ~70% by end-2026? Make-or-break of the glass-cloth bottleneck thesis. Sell-side EPS NT$6-8 in 2026 / ~NT$10 in 2027 (Collyer Bridge).
• Nittobo E-glass exit timeline — faster exit = bigger LDK gap; delayed = thesis softens.
• NVIDIA PCB-replacement for Amphenol overpass — confirms Tripod / Victory Giant volume-per-rack uplift.
• SEMCO W1.6T order customer identity — Google v8e most likely per Jukan's EMIB reporting.
• Silicon capacitor segment disclosure gaps — AP Memory does not publish a silicon-cap segment split (the #1 valuation risk); TSMC's silicon-cap business is sold inside the foundry package, not separately reported; SEMCO silicon-cap margin profile assumed 30% NI pending Citi/guidance confirmation.
• CPO adoption risk — CPO has been "2 years away for 5 years"; 1.6T pluggable optics narrow its power advantage; hyperscalers have paused and restarted programs. Watch for slip pushing the TAM right. TSMC COUPE is the insourced-at-TSMC SiPh play that could shrink the merchant OSAT opportunity.
• Photonic interconnect integration into the PCB stack (2027-2028) — co-packaged optics and in-package silicon photonics displace a fraction of the highest-loss traces; net neutral-to-slightly-positive for advanced PCB demand, positive for highest-grade laminate.

Cycle position dashboard (per ai-server-pcb-primer, current as of the May 2026 sources)

Signal	Current	Reading
CCL utilization (premium grade)	>85%	Tight
Glass cloth utilization (LDK/E-thin)	>90%	Very tight
PCB fab utilization (advanced)	80-90%	Tight
PCB fab utilization (commodity)	60-70%	Soft (irrelevant for AI thesis)
Drill bit consumption	All-time high	Tight
PCB ASP (advanced HLC)	Rising	Pricing power flowing
Lead times (CCL, premium)	8-14 weeks (vs 4-6 normal)	Tight
Inventory days (premium CCL)	Below seasonal	Tight
Capacity announcements	Multiple, but not yet shipping	Lagged

Cycle read: mid-2nd inning of a 2-3 year up-cycle in the materials tier; 4th-5th inning in the named PCB fabricator tier. Materials capacity comes online slower (12-24 month lag), so tightness lasts longer; PCB fab capacity comes online faster (12-18 months), so named-fabricator pricing power wears off earlier. The Cu-wiring-resin sub-layer reads as mid-cycle leaning expensive — fabricators at all-time-high revenue and multiples; chemistry suppliers at all-time-high multiples but lagging revenue.

Trough signals: CCL utilization drops below 70%; lead times return to 4-6 weeks; glass cloth spot prices stabilize. Peak signals: hyperscaler capex guidance flattens; rack-per-quarter shipments plateau; second-tier Chinese fabs achieve advanced HDI qualification at scale.

Leading indicators to monitor quarterly (Cu-wiring-resin sub-layer)

• Quarterly NVIDIA data-center revenue (orders → ~6-month lag to substrate consumption).
• Ibiden / Shinko / Unimicron quarterly utilization rates (>90% utilization is sold-out, signals continued pricing).
• Mitsui Kinzoku quarterly Cu foil volume index disclosure (management publishes it; MicroThin FY24=100 → FY27 target 141, VSP → 219; revisions are direct cycle signals).
• MEC quarterly CZ-8101 volume disclosure (smaller signal, cleanest pure-play read).

Inflection signals (Cu-wiring-resin roadmap)

• Any Vera-Rubin-class substrate disclosure with sub-3µm line/space → MicroThin and AP-series volume rates re-rate up.
• Any glass-substrate commercial-volume confirmation at Intel or major OEM → ABF resin volume growth rate revises down.
• Any Korean / Chinese H-VLP3 customer qualification announcement → Mitsui Kinzoku HVLP pricing power moderates.
• Any MEC AP-series customer disclosure with sub-roughening regime → MEC multiple re-rates higher.

Standing structural-risk watch (single-vendor concentration)

The most acute structural risk in the entire AI substrate supply chain is Ajinomoto's ABF resin single-vendor position (>90% of advanced organic substrates). A fire at Ajinomoto's Kanagawa plant in 2020 caused a 90-day shortage; a repeat today would halt the AI substrate ramp for a quarter. SABIC's April 2026 PPO outage was the "dress rehearsal" for what a real disruption looks like. Other concentration chokepoints to watch: Mitsui Kinzoku MicroThin Cu foil (>90% at top tier), MEC CZ adhesion chemistry (~100% PC CPU / 70-80% advanced), Taiyo Ink solder resist (~60-70%), Nittobo glass cloth (single-country Japan concentration).

Best sources to follow (sector-wide)

• STF Research (stfbutnou.substack.com) — AI-infra investment angles; has led on PCB/CCL TAM, Taiyo Holdings, Kitagawa Seiki, Q-Glass.
• Collyer Bridge / @illyquid (collyerbridge.com) — APAC AI/semis live tracking; ahead on Fulltech, Nittobo, Victory Giant, Intel supply chain.
• Global Tech Research (globaltechresearch.substack.com) — NVIDIA-specific PCB/CCL design-change tracking (GB300 / Vera Rubin).
• Fabricated Knowledge — bonding equipment + advanced packaging value-chain economics.
• Acid Investments — Asia hardware quick-idea posts.
• Twitter / X — @jukan05 (EMIB / silicon cap), @zephyr_z9 (AI & chips bottlenecks), @QQ_Timmy and @LinQingV / Macro_Lin (CCL / PPO / glass cloth squeeze, best Mandarin source), @aleabitoreddit (Serenity, glass substrate), @Mike10947310. Note auth: unauthenticated direct-URL tweet fetches work; timeline scrolling / search require ct0 cookie (Pink to re-auth x.com).
• TrendForce — quarterly OSAT ranking, CoWoS capacity, glass-substrate ecosystem maps.
• Mark Lapedus, SemiAnalysis, Yole, LightCounting, DigiTimes — OSAT / RF-FEM / optical TAM and roadmap.

Sources

The Advanced Packaging & Substrates coverage is built from a stack of vault primers, source notes, a head-to-head comparison, and two raw social scrapes. The list below consolidates every author, publication, and external reference cited across those files. Where a source has (or warrants) a page under _sources/, it is linked as source-handle; where the citation is a one-off institution or a sell-side note with no recurring presence, it is listed plain.

Substack / independent research authors

• STF Research (source-stf-research) — stfbutnou.substack.com. The single most-cited source across the cluster. Specific pieces referenced: Kitagawa Seiki: Hidden Champion Pressing the AI Era (Mar 16, 2026 — flags M9 + Q-Glass as Vera Rubin material; mirror at KB/raw/substack-archive/stf-research/2026-03-16-kitagawa-seiki-hidden-champion-pressing-ai-era.md); Taiyo Holdings: Quantifying Solder Mask Demand (Jan 31, 2026 — substrate area progression Hopper 3,025mm² → Blackwell 5,625mm² → Rubin 8,100mm²); GS Aggressively Revises Up AI PCB/CCL TAM Targets (Jan 7, 2026 — AI PCB TAM $26.6B / AI CCL TAM $18.3B for 2027; mirror at KB/raw/substack-archive/stf-research/2026-01-07-gs-aggressively-revises-up-ai-pcb-ccl-tam.md).
• Collyer Bridge / @illyquid (source-collyer-bridge) — collyerbridge.com. Intel Supply Chain Ideas (Apr 26, 2026 — KB/raw/substack-archive/illyquid/2026-04-26-intel-supply-chain-ideas.md, carrying the jukan05 quote on Intel substrate / T-glass cost headwind); Small Parts, Big Cycle (May 28, 2026 — silicon capacitor cycle); Tripod NVSwitch-primary and Victory Giant NVSwitch share-gain research; Fulltech EPS estimates (NT$6-8 in 2026 / ~NT$10 in 2027); Unitika named as alt glass-cloth play. Chat scrape at ~/claude/output/sectors/collyer-bridge-chat-2026-05-28.md.
• Fabricated Knowledge (source-fabricated-knowledge) — fabricatedknowledge.com. Bonding equipment + advanced packaging coverage; industry framing and value-chain economics. Also the house-style anchor for the primers (the SiP/OSAT primer is written "in the Fabricated Knowledge / SemiAnalysis register").
• SemiAnalysis (source-semianalysis) — newsletter.semianalysis.com. CoWoS / HBM supply chain; advanced packaging series.
• Mark Lapedus (source-mark-lapedus) — marklapedus.substack.com / substack.com/@marklapedus. OSAT rankings, ASE CoWoP, US advanced-packaging consortium.
• PhotonCap (source-photoncap) — bonding equipment scenario mapping; has covered AMAT / BESI / EVG / ASMPT.
• Vik's Newsletter — flagged in the glass-substrate primer as a source that has "led on adjacent semiconductor supply chain stories" to watch for glass-substrate coverage.

Twitter / X authors

• Jukan @jukan05 (source-jukan05) — primary fintwit voice on silicon capacitors and Intel EMIB. Specific posts: the May 28, 2026 "Why Are Silicon Capacitors Becoming Important? And Why Is SEMCO's Stock Surging?" thread (https://x.com/jukan05/status/2059967125020934181, 46.5K views) with the turnkey-substrate-plus-silicon-cap bargaining-power framing; Google v8e TPU / Amazon Trainium EMIB reporting; the Intel substrate / T-glass cost-headwind quote mirrored via Collyer Bridge.
• Zephyr @zephyr_z9 (source-zephyr-z9) — independent "AI & Chips" analyst (bio: "AI & Chips | Not Investment Advice | DYOD"). May 24, 2026 "PSA for Bottleneck bois" post calling silicon capacitor supply tightness (Murata / SEMCO / AP Memory highest exposure). Note the disambiguation: Zephyr is NOT affiliated with Citrini Research — the "Z from Citrini" framing was a conflation.
• Citrini Research @Citrini (source-citrini) — x.com/Citrini, bio "Thematic, Cross-Asset Investment Research." Cited mainly to record the negative: no silicon capacitor / MLCC / SEMCO / AP Memory / Murata content in the visible feed as of the May 28 scrape.
• @aleabitoreddit (Serenity) (source-serenity) — Twitter/X. Carried the TrendForce glass-substrate "leading players" name-drop (2026-05-11) that named the same 9 listed players the primer already mapped; earlier called LPKF at ~$150m market cap "early in the year."

Sell-side, market-research, and institutional sources

• Goldman Sachs — January 2026 AI PCB / CCL TAM revision (via STF Research): AI PCB TAM $26.6B in 2027 (from $17.4B), AI CCL TAM $18.3B (from $8.0B); Murata sell-side meeting May 27, 2026 (Murata acknowledges TSMC / SEMCO / Murata all have silicon capacitor tech).
• Citi — research note on SEMCO silicon capacitor revenue: FY27E W609bn / FY28E W905bn, anchored by a W1.6T two-year supply order (Jan 2027–Dec 2028).
• TrendForce (source-trendforce) — trendforce.com. Top-10 OSAT ranking (global revenue US$41.6B in 2024, +3% YoY); CoWoS capacity updates; the May 2026 glass-substrate "leading players" report (LPKF, Corning, AGC, NEG, Lam Research, Disco, SUSS MicroTec, ONTO, KLAC; underlying report also names SCHOTT and EV Group).
• The Elec — May 20, 2026: SEMCO supplies silicon capacitors to Marvell.
• Yole Group (source-yole) — yolegroup.com. RF FEM teardown reports; silicon-photonics market data; RF FEM TAM US$29B (2025) → US$54B (2030), ~13% CAGR (with Mordor).
• LightCounting — lightcounting.com. Optical transceiver TAM and roadmap.
• DigiTimes — digitimes.com. Taiwan-centric OSAT and SiPh news; ShunSin / Foxconn coverage.
• Mordor Intelligence — RF FEM market sizing (cited alongside Yole).
• Dongguan Securities — Chinese MLCC initiation (~/claude/output/sectors/dongguan-mlcc-initiation-2026-03-25.md).
• Nippon-IBR — Dec 2025 disclosure that MEC's CZ-8101 qualified into CoWoS chiplet packaging.
• Global Tech Research — April 2026 supply story: NVIDIA evaluating a PCB-based replacement for Amphenol's overpass connector.
• Taiwan Optical Electronics — forecast of a 2 million meters/month LDK2 glass-cloth supply gap by 2H26.
• Morningstar / MarketScreener / Yahoo Finance / StockAnalysis / Investing.com — financial data and consensus for the AGC / NEG / Hoya showdown (full URL list reproduced on 5201-vs-5214-vs-7741-showdown).

Company and primary-disclosure sources

• Intel — GlassCore announcement (Sept 2023); Q1 2026 earnings substrate / T-glass / memory cost commentary (Apr 24, 2026); Intel EMIB roadmap (scale-up from 2027); AP Memory named Intel EMIB first-qualified-supplier (May 21, 2026).
• Company IR / filings — Ibiden (Oono Phase 1+2 capex disclosure), Mitsui Kinzoku (Cu-foil volume index; FY26 May 13 guide), MEC (CZ-8101 / AP-series disclosures), AGC / NEG / Hoya Yuho and IR materials, AP Memory (6531) disclosed S-SiCap / IPC product lines.
• imec — co-development partner on Taiyo Holdings FPIM (Fine Pitch Insulating Material) for Rubin HBM4 RDL.

Consolidated vault source files (this sector's inputs)

• packaging-glass-substrate-primer — KB/wiki/packaging-glass-substrate-primer.md (glass-core IC substrate primer; TGV bottleneck thesis)
• glass-substrate-trendforce-2026-05-11 — KB/wiki/glass-substrate-trendforce-2026-05-11.md (TrendForce / Serenity validation source-note)
• silicon-capacitor-primer-2026-05-28 — KB/wiki/silicon-capacitor-primer-2026-05-28.md
• sip-osat-rf-primer — KB/wiki/sip-osat-rf-primer.md
• cu-wiring-resin-primer — KB/wiki/cu-wiring-resin-primer.md
• ai-server-pcb-primer — KB/wiki/ai-server-pcb-primer.md
• cu-resin-swarm-incentive-screen — KB/wiki/themes/cu-resin-swarm-incentive-screen.md
• 5201-vs-5214-vs-7741-showdown — KB/wiki/_compare/5201-vs-5214-vs-7741-showdown.md
• passives-twitter-scrape-2026-05-28 — KB/wiki/passives-twitter-scrape-2026-05-28.md

Cross-referenced vault ticker / dossier pages

These are not external sources but the canonical ticker pages and dossiers the cluster builds on: 8027 (E&R Engineering — TGV laser; full deep-dive + mgmt DD), ATS (AT&S), 5201 (AGC), 5214 (NEG), 7741 (Hoya), LPKF, ONTO, 6531 (AP Memory profile), 4971 / 4062 / 5706 (MEC / Ibiden / Mitsui Kinzoku deep-dives, mgmt-dd, checklists), 002476 (Victory Giant), 6278 (Union Tool). Supporting research files outside the wiki: the MLCC sector deep-dive handoff (~/claude/output/handoff/mlcc-sector-deep-dive-handoff.md), the Capacitor Dossier (KB/raw/mlcc-research/capacitor-dossier-2026-04.pdf), the non-MLCC capacitor primer handoff, the SEMCO swarm files (~/claude/output/{profile,deep-dive,mgmt-dd,checklist}/009150-ks-*.md), and the Vinatech profile (~/claude/output/profile/006440-ks-profile.md, correct ticker 126340.KQ).

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Consolidation queue (merged 2026-05-30 — section-scoped rebuild)

Industry-wide content folded in from these source files. They stay live pending Pink's archive confirm.

• [ ] packaging-glass-substrate-primer.md
• [ ] glass-substrate-trendforce-2026-05-11.md
• [ ] silicon-capacitor-primer-2026-05-28.md
• [ ] sip-osat-rf-primer.md
• [ ] cu-wiring-resin-primer.md
• [ ] ai-server-pcb-primer.md
• [ ] themes/cu-resin-swarm-incentive-screen.md
• [ ] _compare/5201-vs-5214-vs-7741-showdown.md
• [ ] passives-twitter-scrape-2026-05-28.md